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| author | H.J. Lu <hjl.tools@gmail.com> | 2018-09-17 06:11:54 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2018-09-17 06:12:06 -0700 |
| commit | 6fa52824c316091c2beb22fceed9ba96d17f37c4 (patch) | |
| tree | fb131a58000e26579d21c2775e76b173fe5ff832 /opcodes/ChangeLog | |
| parent | 8588b356927dabd582d1d67f87a161027cb2aed1 (diff) | |
| download | gdb-6fa52824c316091c2beb22fceed9ba96d17f37c4.zip gdb-6fa52824c316091c2beb22fceed9ba96d17f37c4.tar.gz gdb-6fa52824c316091c2beb22fceed9ba96d17f37c4.tar.bz2 | |
x86: Replace VexW=3 with VexWIG
* i386-opc.tbl (VexWIG): New.
Replace VexW=3 with VexWIG.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ca03df8..e307ee6 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2018-09-17 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl (VexWIG): New. + Replace VexW=3 with VexWIG. + 2018-09-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss. |