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| author | Jan Beulich <jbeulich@novell.com> | 2017-02-28 10:53:35 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2017-02-28 10:53:35 +0100 |
| commit | 15c7c1d8a535000e94ed36f4259d0ede32001408 (patch) | |
| tree | f7cb2504df939990ac7118de6862d57590ca591c /opcodes/ChangeLog | |
| parent | 4ef97a1b459849ad190244c36b36d45bdd078030 (diff) | |
| download | gdb-15c7c1d8a535000e94ed36f4259d0ede32001408.zip gdb-15c7c1d8a535000e94ed36f4259d0ede32001408.tar.gz gdb-15c7c1d8a535000e94ed36f4259d0ede32001408.tar.bz2 | |
x86: fix handling of 64-bit operand size VPCMPESTR{I,M}
Just like REX.W affects operand size of the implicit rAX/rDX inputs to
PCMPESTR{I,M}, VEX.W does for VPCMPESTR{I,M}. Allow Q or L suffixes on
the instructions.
Similarly the disassembler needs to be adjusted to no longer require
VEX.W to be zero for the instructions to be valid, and to emit proper
suffixes.
Note, however, that this doesn't address the problem of there being no
way to control (at least) {,E}VEX.W for 32- or 16-bit code. Nor does it
address the problem of the many WIG instructions not getting properly
disassembled when VEX.W=1.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 2be1361..4eb33bc 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,15 @@ +2017-02-28 Jan Beulich <jbeulich@suse.com> + + * i386-dis.c (PCMPESTR_Fixup): New. + (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete. + (prefix_table): Use PCMPESTR_Fixup. + (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use + PCMPESTR_Fixup. + (vex_w_table): Delete VPCMPESTR{I,M} entries. + * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm): + Split 64-bit and non-64-bit variants. + * opcodes/i386-tbl.h: Re-generate. + 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) |