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authorAndrew Pinski <apinski@cavium.com>2011-12-08 20:47:27 +0000
committerAndrew Pinski <apinski@cavium.com>2011-12-08 20:47:27 +0000
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2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * archures.c (bfd_mach_mips_octeon2): New macro * bfd-in2.h: Regenerate. * cpu-mips.c (I_mipsocteon2): New enum value. (arch_info_struct): Add bfd_mach_mips_octeon2. * elfxx-mips.c (_bfd_elf_mips_mach): Support E_MIPS_MACH_OCTEON2. (mips_set_isa_flags): Add bfd_mach_mips_octeon2. (mips_mach_extensions): Add bfd_mach_mips_octeon2. gas: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * tc-mips.c (CPU_IS_OCTEON): Add Octeon2. (mips_cpu_info_table): Add Octeon2. * doc/c-mips.texi: Document octeon2 as an acceptable value for -march=. gas/testsuite: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * gas/mips/mips.exp: Add Octeon2 for an architecture. Run octeon2 test. * gas/mips/octeon2.d: New file. * gas/mips/octeon2.s: New file. include/opcode: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2. (INSN_OCTEON2): New macro. (CPU_OCTEON2): New macro. (OPCODE_IS_MEMBER): Add Octeon2. opcodes: 2011-12-08 Andrew Pinski <apinski@cavium.com> Adam Nemet <anemet@caviumnetworks.com> * mips-dis.c (mips_arch_choices): Add Octeon2. For "octeon+", just include OcteonP for the insn. * mips-opc.c (IOCT): Include Octeon2. (IOCTP): Include Octeon2. (IOCT2): New macro. (mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad", "ladd", "lai", "laid", "las", "lasd", "law", "lawd". Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard loads are, and add IOCT2 to them. Add "lbx" and "lhux". Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00", "qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03". Add "zcb" and "zcbt".
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+2011-12-08 Andrew Pinski <apinski@cavium.com>
+ Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips-dis.c (mips_arch_choices): Add Octeon2.
+ For "octeon+", just include OcteonP for the insn.
+ * mips-opc.c (IOCT): Include Octeon2.
+ (IOCTP): Include Octeon2.
+ (IOCT2): New macro.
+ (mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad",
+ "ladd", "lai", "laid", "las", "lasd", "law", "lawd".
+ Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard
+ loads are, and add IOCT2 to them.
+ Add "lbx" and "lhux".
+ Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00",
+ "qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03".
+ Add "zcb" and "zcbt".
+
2011-11-29 Andrew Pinski <apinski@cavium.com>
* mips-dis.c (mips_arch_choices): Add Octeon+.