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authorJan Beulich <jbeulich@suse.com>2019-12-27 09:38:34 +0100
committerJan Beulich <jbeulich@suse.com>2019-12-27 09:38:34 +0100
commit376cd056100dff2d6fc842aa013d0bbffdef363d (patch)
tree2fb3cf2b8cfcc1a3fe9cdda133e21fa0e4146377 /opcodes/ChangeLog
parent48bcea9f48cce70005307befbc604de3618bbaf7 (diff)
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x86-64: fix Intel64 handling of branch with data16 prefix
The expectation of x86-64-branch-3 for "call" / "jmp" with an obvious direct destination to translate to an indirect _far_ branch is plain wrong. The operand size prefix should have no effect at all on the interpretation of the operand. The main underlying issue here is that the Intel64 templates of the direct branches don't include Disp16, yet various assumptions exist that it would always be there when there's also Disp32/Disp32S, toggled by the operand size prefix (which is being ignored by direct branches in Intel64 mode). Along these lines it was also wrong to base the displacement width decision solely on the operand size prefix: REX.W cancels this effect and hence needs taking into consideration, too. A disassembler change is needed here as well: XBEGIN was wrongly treated the same as direct CALL/JMP, which isn't the case - the operand size prefix does affect displacement size there, it's merely ignored when it comes to updating [ER]IP.
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2019-12-27 Jan Beulich <jbeulich@suse.com>
+ * i386-dis.c (Jdqw): Define.
+ (dqw_mode): Adjust associated comment.
+ (rm_table): Use Jdqw for XBEGIN.
+ (OP_J): Handle dqw_mode.
+
+2019-12-27 Jan Beulich <jbeulich@suse.com>
+
* i386-gen.c (process_i386_operand_type): Don't set Disp32 for
Cpu64 templates.
* i386-opc.tbl (mov): Fold two templates.