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| author | Jan Beulich <jbeulich@suse.com> | 2019-07-01 08:31:14 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2019-07-01 08:31:14 +0200 |
| commit | a0a1771e895e6606a2a795c407e20aed73f69bd9 (patch) | |
| tree | 9b75ffcdaa3d8b5f343c148821ddb4da987aa88d /opcodes/ChangeLog | |
| parent | cd546e7bd2832c882e69809fdbeb7b376b62039e (diff) | |
| download | gdb-a0a1771e895e6606a2a795c407e20aed73f69bd9.zip gdb-a0a1771e895e6606a2a795c407e20aed73f69bd9.tar.gz gdb-a0a1771e895e6606a2a795c407e20aed73f69bd9.tar.bz2 | |
x86: optimize EVEX packed integer logical instructions
As long as there's no write mask as well as no broadcast, and as long
as the scaled Disp8 wouldn't result in a shorter EVEX encoding, encode
VPAND{D,Q}, VPANDN{D,Q}, VPOR{D,Q}, and VPXOR{D,Q} acting on only the
lower 16 XMM/YMM registers using their VEX equivalents with -O1.
Also take the opportunity and avoid looping twice over all operands
when dealing with memory-with-displacement ones.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a7322ae..c6a713b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2019-07-01 Jan Beulich <jbeulich@suse.com> + * i386-opc.tbl (and, or): Add Optimize to forms allowing two + register operands. + * i386-tbl.h: Re-generate. + +2019-07-01 Jan Beulich <jbeulich@suse.com> + * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq. * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq, vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors. |