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authorJeff Law <law@redhat.com>1996-08-23 15:41:30 +0000
committerJeff Law <law@redhat.com>1996-08-23 15:41:30 +0000
commit4be84c49517144c93dcce13ef5489984b7ea0dad (patch)
tree87bea275c4b63f0d59d2936d82bfe590b82030dc /opcodes/ChangeLog
parent26b3dc44a5445fbb7e3b2a0677a43d08c91cfa0d (diff)
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* v850-opc.c (v850_operands): D6 -> DS7. References changed.
Add D8 for 8-bit unsigned field in short load/store insns. (IF4A, IF4D): These both need two registers. (IF4C, IF4D): Define. Use 8-bit unsigned field. (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand for "ldsr" and "stsr". * v850-opc.c (v850_operands): 3-bit immediate for bit insns is unsigned. Fixing up the parser again.
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diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
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--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,7 +1,14 @@
start-sanitize-v850
Fri Aug 23 00:27:01 1996 Jeffrey A Law (law@cygnus.com)
- * v850-opc.c (v850_operansd): 3-bit immediate for bit insns
+ * v850-opc.c (v850_operands): D6 -> DS7. References changed.
+ Add D8 for 8-bit unsigned field in short load/store insns.
+ (IF4A, IF4D): These both need two registers.
+ (IF4C, IF4D): Define. Use 8-bit unsigned field.
+ (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use
+ IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand
+ for "ldsr" and "stsr".
+ * v850-opc.c (v850_operands): 3-bit immediate for bit insns
is unsigned.
* v850-opc.c (v850_opcodes): Correct short store half (sst.h) and