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| author | Jan Beulich <jbeulich@novell.com> | 2018-11-06 11:42:08 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2018-11-06 11:42:08 +0100 |
| commit | fd71a3756e2dd1eae116d77dc5ec58391c4840d8 (patch) | |
| tree | fe9cd28cf8b0c1c602df84a87b16770f783e008f /opcodes/ChangeLog | |
| parent | 563c7eef61a1835973b857eaa7372ec66fc91d64 (diff) | |
| download | gdb-fd71a3756e2dd1eae116d77dc5ec58391c4840d8.zip gdb-fd71a3756e2dd1eae116d77dc5ec58391c4840d8.tar.gz gdb-fd71a3756e2dd1eae116d77dc5ec58391c4840d8.tar.bz2 | |
x86: fix various non-LIG templates
Quite a few templates were marked LIG while really the insns aren't.
Introduce descriptive shorthands once again, instead of continuing to
use the less legible original forms.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8137672..444ab05 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,15 @@ 2018-11-06 Jan Beulich <jbeulich@suse.com> + * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256, + EVex512, EVexLIG, EVexDYN): New. + (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM + insns): Use Vex128 instead of Vex=3 (aka VexLIG). + (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead + of EVex=4 (aka EVexLIG). + * i386-tbl.h: Re-generate. + +2018-11-06 Jan Beulich <jbeulich@suse.com> + * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms. (vpmaxub): Re-order attributes on AVX512BW flavor. * i386-tbl.h: Re-generate. |