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| author | Nick Clifton <nickc@redhat.com> | 2009-12-17 09:52:18 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2009-12-17 09:52:18 +0000 |
| commit | ff4a8d2b939133ea12e8994ff1f83d3a8e17baa2 (patch) | |
| tree | 8c2067c8669ec9c306998941830cb370617d77ad /opcodes/ChangeLog | |
| parent | 32af9f6e558c4f6bb55d36a317d2ec43b29d4bb6 (diff) | |
| download | gdb-ff4a8d2b939133ea12e8994ff1f83d3a8e17baa2.zip gdb-ff4a8d2b939133ea12e8994ff1f83d3a8e17baa2.tar.gz gdb-ff4a8d2b939133ea12e8994ff1f83d3a8e17baa2.tar.bz2 | |
PR binutils/10924
* config/tc-arm.c (do_ldstv4): Do not allow r15 as the destination
register.
(do_mrs): Likewise.
(do_mul): Likewise.
* arm-dis.c: Add support for %<>ru and %<>rU formats to enforce
unique register numbers. Extend support for %<>R format to
thumb32 and coprocessor instructions.
* gas/arm/unpredictable.s: Add more unpredictable instructions.
* gas/arm/unpredictable.d: Add expected disassemblies.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ad7d7b2..222603e 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2009-12-17 Nick Clifton <nickc@redhat.com> + + PR binutils/10924 + * arm-dis.c: Add support for %<>ru and %<>rU formats to enforce + unique register numbers. Extend support for %<>R format to + thumb32 and coprocessor instructions. + 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove ByteOkIntel. |