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| author | Jan Beulich <jbeulich@novell.com> | 2018-03-22 08:31:43 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2018-03-22 08:31:43 +0100 |
| commit | d6793fa1acf384a93c83db6eb916e3b9eedd9ef4 (patch) | |
| tree | 8c6ac3bc26803c338b3ae5a9edce2ff5f025f7e6 /opcodes/ChangeLog | |
| parent | f776822506b417ce25170c67c33cc05870b37adf (diff) | |
| download | gdb-d6793fa1acf384a93c83db6eb916e3b9eedd9ef4.zip gdb-d6793fa1acf384a93c83db6eb916e3b9eedd9ef4.tar.gz gdb-d6793fa1acf384a93c83db6eb916e3b9eedd9ef4.tar.bz2 | |
x86/Intel: fix fallout from earlier template folding
While many templates allowing multiple suitably matching XMM/YMM/ZMM
operand sizes can be folded, a few need to be split in order to not
wrongly accept "xmmword ptr" operands when only XMM registers are
permitted (and memory operands are more narrow). Add a test case
validating this.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 12070dc..c33e5a0 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,12 @@ 2018-03-22 Jan Beulich <jbeulich@suse.com> + * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate + templates allowing memory operands and folded ones for register + only flavors. + * i386-tlb.h: Re-generate. + +2018-03-22 Jan Beulich <jbeulich@suse.com> + * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and 256-bit templates. Drop redundant leftover Disp<N>. * i386-tlb.h: Re-generate. |