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| author | Sudakshina Das <sudi.das@arm.com> | 2018-11-12 13:29:38 +0000 |
|---|---|---|
| committer | Sudakshina Das <sudi.das@arm.com> | 2018-11-12 13:29:38 +0000 |
| commit | 3a0f69be5589d351453afebd0974992cff3ee4d1 (patch) | |
| tree | e9cc9c1fd12e544636d370692c0f142e4e6f2eba /multilib.am | |
| parent | 70f3d23af74dd6a1f90aec8748424cf0b5a953a5 (diff) | |
| download | gdb-3a0f69be5589d351453afebd0974992cff3ee4d1.zip gdb-3a0f69be5589d351453afebd0974992cff3ee4d1.tar.gz gdb-3a0f69be5589d351453afebd0974992cff3ee4d1.tar.bz2 | |
[BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds all the data cache instructions that are part of this
extension:
- DC IGVAC, Xt
- DC IGSW, Xt
- DC CGSW, Xt
- DC CIGSW, Xt
- DC CGVAC, Xt
- DC CGVAP, Xt
- DC CGVADP, Xt
- DC CIGVAC, Xt
- DC GVA, Xt
- DC IGDVAC, Xt
- DC IGDSW, Xt
- DC CGDSW, Xt
- DC CIGDSW, Xt
- DC CGDVAC, Xt
- DC CGDVAP, Xt
- DC CGDVADP, Xt
- DC CIGDVAC, Xt
- DC GZVA, Xt
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): New entries for
IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
CIGDVAC and GZVA.
(aarch64_sys_ins_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test IGVAC, IGSW,
CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
CIGDVAC and GZVA with DC.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
Diffstat (limited to 'multilib.am')
0 files changed, 0 insertions, 0 deletions