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| author | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 17:09:59 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 17:09:59 +0100 |
| commit | bb7eff5206e4795ac79c177a80fe9f4630aaf730 (patch) | |
| tree | ebea7c8fc80d1fbca2c49b1b8988e9a8816b6042 /ld | |
| parent | f2a5c4f5af38b146f0bc7e1407e422ac292f9da7 (diff) | |
| download | gdb-bb7eff5206e4795ac79c177a80fe9f4630aaf730.zip gdb-bb7eff5206e4795ac79c177a80fe9f4630aaf730.tar.gz gdb-bb7eff5206e4795ac79c177a80fe9f4630aaf730.tar.bz2 | |
[AArch64] Add SVE condition codes
SVE defines new names for existing NZCV conditions, to reflect the
result of instructions like PTEST. This patch adds support for these
names.
The patch also adds comments to the disassembly output to show the
alternative names of a condition code. For example:
cinv x0, x1, cc
becomes:
cinv x0, x1, cc // cc = lo, ul, last
and:
b.cc f0 <...>
becomes:
b.cc f0 <...> // b.lo, b.ul, b.last
Doing this for the SVE names follows the practice recommended by the
SVE specification and is definitely useful when reading SVE code.
If the feeling is that it's too distracting elsewhere, we could add
an option to turn it off.
include/
* opcode/aarch64.h (aarch64_cond): Bump array size to 4.
opcodes/
* aarch64-dis.c (remove_dot_suffix): New function, split out from...
(print_mnemonic_name): ...here.
(print_comment): New function.
(print_aarch64_insn): Call it.
* aarch64-opc.c (aarch64_conds): Add SVE names.
(aarch64_print_operand): Print alternative condition names in
a comment.
gas/
* config/tc-aarch64.c (opcode_lookup): Search for the end of
a condition name, rather than assuming that it will have exactly
2 characters.
(parse_operands): Likewise.
* testsuite/gas/aarch64/alias.d: Add new condition-code comments
to the expected output.
* testsuite/gas/aarch64/beq_1.d: Likewise.
* testsuite/gas/aarch64/float-fp16.d: Likewise.
* testsuite/gas/aarch64/int-insns.d: Likewise.
* testsuite/gas/aarch64/no-aliases.d: Likewise.
* testsuite/gas/aarch64/programmer-friendly.d: Likewise.
* testsuite/gas/aarch64/reloc-insn.d: Likewise.
* testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
New test.
ld/
* testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments.
* testsuite/ld-aarch64/weak-undefined.d: Likewise.
Diffstat (limited to 'ld')
| -rw-r--r-- | ld/ChangeLog | 5 | ||||
| -rw-r--r-- | ld/testsuite/ld-aarch64/emit-relocs-280.d | 4 | ||||
| -rw-r--r-- | ld/testsuite/ld-aarch64/weak-undefined.d | 12 |
3 files changed, 13 insertions, 8 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog index b9b335d..01c8a04 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,8 @@ +2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + + * testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments. + * testsuite/ld-aarch64/weak-undefined.d: Likewise. + 2016-09-20 Andrew Burgess <andrew.burgess@embecosm.com> * ld.texinfo (Input Section Basics): Expand the description of diff --git a/ld/testsuite/ld-aarch64/emit-relocs-280.d b/ld/testsuite/ld-aarch64/emit-relocs-280.d index 9b954ff..85f5c98 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-280.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-280.d @@ -6,7 +6,7 @@ +10004: 8a000000 and .* +10008: 8a000000 and .* +1000c: 8a000000 and .* - +10010: 54fdff80 b.eq c000 <target> + +10010: 54fdff80 b.eq c000 <target> // .* +10010: R_AARCH64_CONDBR19 target - +10014: 54fdffe0 b.eq c010 <target\+0x10> + +10014: 54fdffe0 b.eq c010 <target\+0x10> // .* +10014: R_AARCH64_CONDBR19 target\+0x10 diff --git a/ld/testsuite/ld-aarch64/weak-undefined.d b/ld/testsuite/ld-aarch64/weak-undefined.d index 22a9860..29ba2e5 100644 --- a/ld/testsuite/ld-aarch64/weak-undefined.d +++ b/ld/testsuite/ld-aarch64/weak-undefined.d @@ -2,13 +2,13 @@ #ld: -Ttext 0xF0000000 -T relocs.ld -e0 --emit-relocs #objdump: -d #... - +f0000000: 54000001 b\.ne f0000000 <main> - +f0000004: 54000000 b\.eq f0000004 <main\+0x4> - +f0000008: 54000002 b\.cs f0000008 <main\+0x8> - +f000000c: 54000003 b\.cc f000000c <main\+0xc> + +f0000000: 54000001 b\.ne f0000000 <main> // .* + +f0000004: 54000000 b\.eq f0000004 <main\+0x4> // .* + +f0000008: 54000002 b\.cs f0000008 <main\+0x8> // .* + +f000000c: 54000003 b\.cc f000000c <main\+0xc> // .* +f0000010: 5400000c b\.gt f0000010 <main\+0x10> - +f0000014: 5400000a b\.ge f0000014 <main\+0x14> - +f0000018: 5400000b b\.lt f0000018 <main\+0x18> + +f0000014: 5400000a b\.ge f0000014 <main\+0x14> // .* + +f0000018: 5400000b b\.lt f0000018 <main\+0x18> // .* +f000001c: 5400000d b\.le f000001c <main\+0x1c> +f0000020: d503201f nop +f0000024: d503201f nop |