[PowerPC64] pc-relative TLS relocations

This patch supports using pcrel instructions in TLS code sequences.  A
number of new relocations are needed, gas operand modifiers to
generate those relocations, and new TLS optimisation.  For
optimisation it turns out that the new pcrel GD and LD sequences can
be distinguished from the non-pcrel GD and LD sequences by there being
different relocations on the new sequence.  The final "add ra,rb,13"
on IE sequences similarly needs a new relocation, or as I chose, a
modification of R_PPC64_TLS.  On pcrel IE code, the R_PPC64_TLS points
one byte into the "add" instruction rather than being on the
instruction boundary.

GD:
 pla 3,z@got@tlsgd@pcrel	  # R_PPC64_GOT_TLSGD34
 bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC
  edited to IE
   pld 3,z@got@tprel@pcrel
   add 3,3,13
  edited to LE
   paddi 3,13,z@tprel
   nop

LD:
 pla 3,z@got@tlsld@pcrel	  # R_PPC64_GOT_TLSLD34
 bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC
 ..
 paddi 9,3,z2@dtprel
 pld 10,z3@got@dtprel@pcrel
 add 10,10,3
  edited to LE
   paddi 3,13,0x1000
   nop

IE:
 pld 9,z@got@tprel@pcrel	  # R_PPC64_GOT_TPREL34
 add 3,9,z@tls@pcrel		  # R_PPC64_TLS at insn+1
 ldx 4,9,z@tls@pcrel
 lwax 5,9,z@tls@pcrel
 stdx 5,9,z@tls@pcrel
  edited to LE
  paddi 9,13,z@tprel
  nop
  ld 4,0(9)
  lwa 5,0(9)
  std 5,0(9)

LE:
 paddi 10,13,z@tprel

include/
	* elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34),
	(R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34),
	(R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define.
	(IS_PPC64_TLS_RELOC): Include new tls relocs.
bfd/
	* reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34),
	(BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34),
	(BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34),
	(BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs.
	* elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs.
	(ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs.
	(must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64.
	(ppc64_elf_check_relocs): Support pcrel tls relocs.
	(ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
gas/
	* config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel",
	"got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel".
	(fixup_size, md_assemble): Handle pcrel tls relocs.
	(ppc_force_relocation, ppc_fix_adjustable): Likewise.
	(md_apply_fix, tc_gen_reloc): Likewise.
ld/
	* testsuite/ld-powerpc/tlsgd.d,
	* testsuite/ld-powerpc/tlsgd.s,
	* testsuite/ld-powerpc/tlsie.d,
	* testsuite/ld-powerpc/tlsie.s,
	* testsuite/ld-powerpc/tlsld.d,
	* testsuite/ld-powerpc/tlsld.s: New tests.
	* testsuite/ld-powerpc/powerpc.exp: Run them.

8 files changed, 321 insertions, 0 deletions

diff --git a/ld/ChangeLog b/ld/ChangeLog
index c031b0e..9fcc55c 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,5 +1,15 @@
 2019-07-19  Alan Modra  <amodra@gmail.com>
 
+	* testsuite/ld-powerpc/tlsgd.d,
+	* testsuite/ld-powerpc/tlsgd.s,
+	* testsuite/ld-powerpc/tlsie.d,
+	* testsuite/ld-powerpc/tlsie.s,
+	* testsuite/ld-powerpc/tlsld.d,
+	* testsuite/ld-powerpc/tlsld.s: New tests.
+	* testsuite/ld-powerpc/powerpc.exp: Run them.
+
+2019-07-19  Alan Modra  <amodra@gmail.com>
+
 	* testsuite/ld-powerpc/tlsldopt.d: Rename from tlsld.d.
 	* testsuite/ld-powerpc/tlsldopt.s: Rename from tlsld.s.
 	* testsuite/ld-powerpc/tlsldopt32.d: Rename from tlsld32.d.
diff --git a/ld/testsuite/ld-powerpc/powerpc.exp b/ld/testsuite/ld-powerpc/powerpc.exp
index 508d48e..87a7462 100644
--- a/ld/testsuite/ld-powerpc/powerpc.exp
+++ b/ld/testsuite/ld-powerpc/powerpc.exp
@@ -343,6 +343,9 @@ if [ supports_ppc64 ] then {
     run_dump_test "pr23937"
     run_dump_test "callstub-1"
     run_dump_test "callstub-2"
+    run_dump_test "tlsgd"
+    run_dump_test "tlsld"
+    run_dump_test "tlsie"
 }
 
 run_dump_test "tlsldopt32"
diff --git a/ld/testsuite/ld-powerpc/tlsgd.d b/ld/testsuite/ld-powerpc/tlsgd.d
new file mode 100644
index 0000000..42c9b5f
--- /dev/null
+++ b/ld/testsuite/ld-powerpc/tlsgd.d
@@ -0,0 +1,31 @@
+#source: tlsgd.s
+#as: -a64 -mfuture
+#ld: -melf64ppc
+#objdump: -dr -Mfuture
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+.*:
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(38 6d 90 08|08 90 6d 38) 	addi    r3,r13,-28664
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(38 6d 90 10|10 90 6d 38) 	addi    r3,r13,-28656
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(06 03 ff ff|ff ff 03 06) 	paddi   r3,r13,-28648
+.*:	(38 6d 90 18|18 90 6d 38) 
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(38 6d 90 20|20 90 6d 38) 	addi    r3,r13,-28640
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(38 6d 90 20|20 90 6d 38) 	addi    r3,r13,-28640
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(06 03 ff ff|ff ff 03 06) 	paddi   r3,r13,-28640
+.*:	(38 6d 90 20|20 90 6d 38) 
+.*:	(60 00 00 00|00 00 00 60) 	nop
diff --git a/ld/testsuite/ld-powerpc/tlsgd.s b/ld/testsuite/ld-powerpc/tlsgd.s
new file mode 100644
index 0000000..304bd60
--- /dev/null
+++ b/ld/testsuite/ld-powerpc/tlsgd.s
@@ -0,0 +1,52 @@
+ .section ".tbss","awT",@nobits
+ .p2align 3
+pad: .space 8
+ .global a
+a: .space 8
+ .global b
+b: .space 8
+ .global c
+c: .space 8
+ .global d
+d: .space 8
+
+ .text
+ .globl _start
+_start:
+#Small model OpenPower
+ addi 3,2,.La@toc
+ bl __tls_get_addr(.La@tlsgd)
+ nop
+ .section .toc,"aw",@progbits
+ .p2align 3
+.La:
+ .quad a@dtpmod
+ .quad a@dtprel
+ .text
+
+#Medium mode ELF
+ addis 3,2,b@got@tlsgd@ha
+ addi 3,3,b@got@tlsgd@l
+ bl __tls_get_addr(b@tlsgd)
+ nop
+
+#PCrel
+ pla 3,c@got@tlsgd@pcrel
+ bl __tls_get_addr@notoc(c@tlsgd)
+
+#All of the above using the same symbol
+ addis 3,2,.Ld@toc@ha
+ addi 3,3,.Ld@toc@l
+ bl __tls_get_addr(.Ld@tlsgd)
+ nop
+ .section .toc,"aw",@progbits
+.Ld:
+ .quad d@dtpmod
+ .quad d@dtprel
+ .text
+ addis 3,2,d@got@tlsgd@ha
+ addi 3,3,d@got@tlsgd@l
+ bl __tls_get_addr(d@tlsgd)
+ nop
+ pla 3,d@got@tlsgd@pcrel
+ bl __tls_get_addr@notoc(d@tlsgd)
diff --git a/ld/testsuite/ld-powerpc/tlsie.d b/ld/testsuite/ld-powerpc/tlsie.d
new file mode 100644
index 0000000..79613bd
--- /dev/null
+++ b/ld/testsuite/ld-powerpc/tlsie.d
@@ -0,0 +1,54 @@
+#source: tlsie.s
+#as: -a64 -mfuture
+#ld: -melf64ppc
+#objdump: -dr -Mfuture
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+.*:
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(39 4d 90 08|08 90 4d 39) 	addi    r10,r13,-28664
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(38 6d 90 10|10 90 6d 38) 	addi    r3,r13,-28656
+.*:	(06 03 ff ff|ff ff 03 06) 	paddi   r4,r13,-28648
+.*:	(38 8d 90 18|18 90 8d 38) 
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(39 4d 90 20|20 90 4d 39) 	addi    r10,r13,-28640
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(38 6d 90 20|20 90 6d 38) 	addi    r3,r13,-28640
+.*:	(06 03 ff ff|ff ff 03 06) 	paddi   r30,r13,-28640
+.*:	(3b cd 90 20|20 90 cd 3b) 
+.*:	(7f c3 f3 78|78 f3 c3 7f) 	mr      r3,r30
+.*:	(80 9e 00 00|00 00 9e 80) 	lwz     r4,0\(r30\)
+.*:	(84 9e 00 00|00 00 9e 84) 	lwzu    r4,0\(r30\)
+.*:	(88 be 00 00|00 00 be 88) 	lbz     r5,0\(r30\)
+.*:	(8c be 00 00|00 00 be 8c) 	lbzu    r5,0\(r30\)
+.*:	(90 de 00 00|00 00 de 90) 	stw     r6,0\(r30\)
+.*:	(94 de 00 00|00 00 de 94) 	stwu    r6,0\(r30\)
+.*:	(98 fe 00 00|00 00 fe 98) 	stb     r7,0\(r30\)
+.*:	(9c fe 00 00|00 00 fe 9c) 	stbu    r7,0\(r30\)
+.*:	(a1 1e 00 00|00 00 1e a1) 	lhz     r8,0\(r30\)
+.*:	(a5 1e 00 00|00 00 1e a5) 	lhzu    r8,0\(r30\)
+.*:	(a9 3e 00 00|00 00 3e a9) 	lha     r9,0\(r30\)
+.*:	(ad 3e 00 00|00 00 3e ad) 	lhau    r9,0\(r30\)
+.*:	(b1 5e 00 00|00 00 5e b1) 	sth     r10,0\(r30\)
+.*:	(b5 5e 00 00|00 00 5e b5) 	sthu    r10,0\(r30\)
+.*:	(c1 7e 00 00|00 00 7e c1) 	lfs     f11,0\(r30\)
+.*:	(c5 7e 00 00|00 00 7e c5) 	lfsu    f11,0\(r30\)
+.*:	(c9 9e 00 00|00 00 9e c9) 	lfd     f12,0\(r30\)
+.*:	(cd 9e 00 00|00 00 9e cd) 	lfdu    f12,0\(r30\)
+.*:	(d1 be 00 00|00 00 be d1) 	stfs    f13,0\(r30\)
+.*:	(d5 be 00 00|00 00 be d5) 	stfsu   f13,0\(r30\)
+.*:	(d9 de 00 00|00 00 de d9) 	stfd    f14,0\(r30\)
+.*:	(dd de 00 00|00 00 de dd) 	stfdu   f14,0\(r30\)
+.*:	(e9 fe 00 00|00 00 fe e9) 	ld      r15,0\(r30\)
+.*:	(e9 fe 00 01|01 00 fe e9) 	ldu     r15,0\(r30\)
+.*:	(fa 1e 00 00|00 00 1e fa) 	std     r16,0\(r30\)
+.*:	(fa 1e 00 01|01 00 1e fa) 	stdu    r16,0\(r30\)
+.*:	(ea 3e 00 02|02 00 3e ea) 	lwa     r17,0\(r30\)
diff --git a/ld/testsuite/ld-powerpc/tlsie.s b/ld/testsuite/ld-powerpc/tlsie.s
new file mode 100644
index 0000000..384e7ce
--- /dev/null
+++ b/ld/testsuite/ld-powerpc/tlsie.s
@@ -0,0 +1,77 @@
+ .section ".tbss","awT",@nobits
+ .p2align 3
+pad: .space 8
+ .global a
+a: .space 8
+ .global b
+b: .space 8
+ .global c
+c: .space 8
+ .global d
+d: .space 8
+
+ .text
+ .globl _start
+_start:
+#Small model OpenPower
+ ld 9,.La@toc(2)
+ add 10,9,.La@tls
+ .section .toc,"aw",@progbits
+.La:
+ .quad a@tprel
+ .text
+
+#Medium model ELF
+ addi 9,2,b@got@tprel@ha
+ ld 10,b@got@tprel@l(9)
+ add 3,10,b@tls
+
+#PCrel
+ pld 4,c@got@tprel@pcrel
+ add 4,4,c@tls@pcrel
+
+#All of the above using the same symbol
+ addis 9,2,.Ld@toc@ha
+ ld 9,.Ld@toc@l(9)
+ add 10,9,.Ld@tls
+ .section .toc,"aw",@progbits
+.Ld:
+ .quad d@tprel
+ .text
+ addi 9,2,d@got@tprel@ha
+ ld 31,d@got@tprel@l(9)
+ add 3,31,d@tls
+ pld 30,d@got@tprel@pcrel
+ add 3,30,d@tls@pcrel
+#Note that after optimisation r31 and r30 above have a different value to
+#what they would have without optimisation.  r31 may not even be written.
+#Here are all the other insns that gas/ld accept as the final insn of an
+#IE sequence.  The r30 value below will be different after optimisation
+#for the non-update forms.
+ lwzx 4,30,d@tls@pcrel
+ lwzux 4,30,d@tls@pcrel
+ lbzx 5,30,d@tls@pcrel
+ lbzux 5,30,d@tls@pcrel
+ stwx 6,30,d@tls@pcrel
+ stwux 6,30,d@tls@pcrel
+ stbx 7,30,d@tls@pcrel
+ stbux 7,30,d@tls@pcrel
+ lhzx 8,30,d@tls@pcrel
+ lhzux 8,30,d@tls@pcrel
+ lhax 9,30,d@tls@pcrel
+ lhaux 9,30,d@tls@pcrel
+ sthx 10,30,d@tls@pcrel
+ sthux 10,30,d@tls@pcrel
+ lfsx 11,30,d@tls@pcrel
+ lfsux 11,30,d@tls@pcrel
+ lfdx 12,30,d@tls@pcrel
+ lfdux 12,30,d@tls@pcrel
+ stfsx 13,30,d@tls@pcrel
+ stfsux 13,30,d@tls@pcrel
+ stfdx 14,30,d@tls@pcrel
+ stfdux 14,30,d@tls@pcrel
+ ldx 15,30,d@tls@pcrel
+ ldux 15,30,d@tls@pcrel
+ stdx 16,30,d@tls@pcrel
+ stdux 16,30,d@tls@pcrel
+ lwax 17,30,d@tls@pcrel
diff --git a/ld/testsuite/ld-powerpc/tlsld.d b/ld/testsuite/ld-powerpc/tlsld.d
new file mode 100644
index 0000000..740b15b
--- /dev/null
+++ b/ld/testsuite/ld-powerpc/tlsld.d
@@ -0,0 +1,36 @@
+#source: tlsld.s
+#as: -a64 -mfuture
+#ld: -melf64ppc
+#objdump: -dr -Mfuture
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+.*:
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(38 6d 10 00|00 10 6d 38) 	addi    r3,r13,4096
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(38 6d 10 00|00 10 6d 38) 	addi    r3,r13,4096
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(06 00 00 00|00 00 00 06) 	paddi   r3,r13,4096
+.*:	(38 6d 10 00|00 10 6d 38) 
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(06 03 ff ff|ff ff 03 06) 	paddi   r9,r3,-32728
+.*:	(39 23 80 28|28 80 23 39) 
+.*:	(04 10 00 01|01 00 10 04) 	pld     r10,65784
+.*:	(e5 40 00 f8|f8 00 40 e5) 
+.*:	(7d 4a 1a 14|14 1a 4a 7d) 	add     r10,r10,r3
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(38 6d 10 00|00 10 6d 38) 	addi    r3,r13,4096
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(38 6d 10 00|00 10 6d 38) 	addi    r3,r13,4096
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(06 00 00 00|00 00 00 06) 	paddi   r3,r13,4096
+.*:	(38 6d 10 00|00 10 6d 38) 
+.*:	(60 00 00 00|00 00 00 60) 	nop
diff --git a/ld/testsuite/ld-powerpc/tlsld.s b/ld/testsuite/ld-powerpc/tlsld.s
new file mode 100644
index 0000000..4ab2630
--- /dev/null
+++ b/ld/testsuite/ld-powerpc/tlsld.s
@@ -0,0 +1,58 @@
+ .section ".tbss","awT",@nobits
+ .p2align 3
+pad: .space 8
+ .global a
+a: .space 8
+ .global b
+b: .space 8
+ .global c
+c: .space 8
+ .global d
+d: .space 8
+z2: .space 8
+z3: .space 8
+
+ .text
+ .globl _start
+_start:
+#Small model OpenPower
+ addi 3,2,.La@toc
+ bl __tls_get_addr(.La@tlsld)
+ nop
+ .section .toc,"aw",@progbits
+ .p2align 3
+.La:
+ .quad a@dtpmod
+ .quad 0
+ .text
+
+#Medium mode ELF
+ addis 3,2,b@got@tlsld@ha
+ addi 3,3,b@got@tlsld@l
+ bl __tls_get_addr(b@tlsld)
+ nop
+
+#PCrel, with dtprel access to vars
+ pla 3,c@got@tlsld@pcrel
+ bl __tls_get_addr@notoc(c@tlsld)
+ paddi 9,3,z2@dtprel
+ pld 10,z3@got@dtprel@pcrel
+ add 10,10,3
+
+#All of the above using the same symbol
+ addis 3,2,.Ld@toc@ha
+ addi 3,3,.Ld@toc@l
+ bl __tls_get_addr(.Ld@tlsld)
+ nop
+ .section .toc,"aw",@progbits
+ .p2align 3
+.Ld:
+ .quad d@dtpmod
+ .quad 0
+ .text
+ addis 3,2,d@got@tlsld@ha
+ addi 3,3,d@got@tlsld@l
+ bl __tls_get_addr(d@tlsld)
+ nop
+ pla 3,d@got@tlsld@pcrel
+ bl __tls_get_addr@notoc(d@tlsld)