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author | Thiemo Seufer <ths@networkno.de> | 2006-11-02 15:20:31 +0000 |
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committer | Thiemo Seufer <ths@networkno.de> | 2006-11-02 15:20:31 +0000 |
commit | b9d58d7191dd79b88a77f91e4b621b60966fd692 (patch) | |
tree | e8bbae938a7817f3f451eac139bcb688ab7b542c /ld | |
parent | 325a4b61ce4789da1e34e8a5af13ccedcbce2f4d (diff) | |
download | gdb-b9d58d7191dd79b88a77f91e4b621b60966fd692.zip gdb-b9d58d7191dd79b88a77f91e4b621b60966fd692.tar.gz gdb-b9d58d7191dd79b88a77f91e4b621b60966fd692.tar.bz2 |
[ bfd/ChangeLog ]
* elf-bfd.h (local_call_stubs): New member.
* elfxx-mips.c (FN_STUB_P, CALL_STUB_P, CALL_FP_STUB_P): New macros.
(mips_elf_calculate_relocation): Handle local mips16 call stubs.
(mips16_stub_section_p): Rename from mips_elf_stub_section_p, use
the new stub macros.
(_bfd_mips_elf_check_relocs): Handle call stubs for code which
mixes mips16 and mips32 functions. Use mips16_stub_section_p. Mark
used stubs with SEC_KEEP. Use the new stub macros.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips16-intermix.d, gas/mips/mips16-intermix.s: New
testcase.
* gas/mips/mips.exp: Run new testcase.
[ ld/testsuite/ChangeLog ]
* ld-mips-elf/mips16-intermix-1.s, ld-mips-elf/mips16-intermix-2.s,
ld-mips-elf/mips16-intermix.d: New testcase.
* ld-mips-elf/mips-elf.exp (mips16_intermix_test): Run new testcases.
Diffstat (limited to 'ld')
-rw-r--r-- | ld/testsuite/ChangeLog | 6 | ||||
-rw-r--r-- | ld/testsuite/ld-mips-elf/mips-elf.exp | 10 | ||||
-rw-r--r-- | ld/testsuite/ld-mips-elf/mips16-intermix-1.s | 104 | ||||
-rw-r--r-- | ld/testsuite/ld-mips-elf/mips16-intermix-2.s | 2631 | ||||
-rw-r--r-- | ld/testsuite/ld-mips-elf/mips16-intermix.d | 132 |
5 files changed, 2883 insertions, 0 deletions
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index 7e8c199..42fd441 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2006-11-01 Thiemo Seufer <ths@mips.com> + + * ld-mips-elf/mips16-intermix-1.s, ld-mips-elf/mips16-intermix-2.s, + ld-mips-elf/mips16-intermix.d: New testcase. + * ld-mips-elf/mips-elf.exp (mips16_intermix_test): Run new testcases. + 2006-10-29 Kaz Kojima <kkojima@rr.iij4u.or.jp> * ld-sh/sh64/abi32.xd, ld-sh/sh64/abi64.xd, ld-sh/sh64/cmpct1.xd, diff --git a/ld/testsuite/ld-mips-elf/mips-elf.exp b/ld/testsuite/ld-mips-elf/mips-elf.exp index f3d4707..5bb5c38 100644 --- a/ld/testsuite/ld-mips-elf/mips-elf.exp +++ b/ld/testsuite/ld-mips-elf/mips-elf.exp @@ -259,3 +259,13 @@ set mips16_call_global_test { } run_ld_link_tests $mips16_call_global_test + +set mips16_intermix_test { + {"Intermixing mips32 and mips16 functions" + "" + "-mips32r2" {mips16-intermix-1.s mips16-intermix-2.s} + {{objdump -t mips16-intermix.d}} + "mips16-intermix"} +} + +run_ld_link_tests $mips16_intermix_test diff --git a/ld/testsuite/ld-mips-elf/mips16-intermix-1.s b/ld/testsuite/ld-mips-elf/mips16-intermix-1.s new file mode 100644 index 0000000..c596619 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/mips16-intermix-1.s @@ -0,0 +1,104 @@ + .text + .align 2 + .globl __start + .set nomips16 + .ent __start +__start: + .frame $sp,56,$31 # vars= 0, regs= 3/2, args= 24, gp= 0 + .mask 0x80030000,-24 + .fmask 0x00f00000,-8 + .set noreorder + .set nomacro + + addiu $sp,$sp,-56 + sw $31,32($sp) + sw $17,28($sp) + sw $16,24($sp) + sdc1 $f22,48($sp) + sdc1 $f20,40($sp) + jal m32_l + move $4,$17 + + move $4,$17 + jal m16_l + move $16,$2 + + addu $16,$16,$2 + jal m32_d + mov.d $f12,$f22 + + addu $16,$16,$2 + jal m16_d + mov.d $f12,$f22 + + move $4,$17 + mfc1 $7,$f22 + mfc1 $6,$f23 + jal m32_ld + addu $16,$16,$2 + + move $4,$17 + mfc1 $7,$f22 + mfc1 $6,$f23 + jal m16_ld + addu $16,$16,$2 + + move $6,$17 + mov.d $f12,$f22 + jal m32_dl + addu $16,$16,$2 + + move $6,$17 + mov.d $f12,$f22 + jal m16_dl + addu $16,$16,$2 + + move $6,$17 + move $7,$17 + sdc1 $f22,16($sp) + mov.d $f12,$f22 + jal m32_dlld + addu $16,$16,$2 + + move $6,$17 + move $7,$17 + mov.d $f12,$f22 + sdc1 $f22,16($sp) + jal m16_dlld + addu $16,$16,$2 + + move $4,$17 + jal m32_d_l + addu $16,$16,$2 + + move $4,$17 + jal m16_d_l + mov.d $f20,$f0 + + move $4,$17 + mfc1 $7,$f22 + mfc1 $6,$f23 + jal f32 + add.d $f20,$f20,$f0 + + move $4,$17 + add.d $f20,$f20,$f0 + mfc1 $7,$f22 + jal f16 + mfc1 $6,$f23 + + add.d $f20,$f20,$f0 + lw $31,32($sp) + trunc.w.d $f0,$f20 + lw $17,28($sp) + mfc1 $3,$f0 + addu $2,$3,$16 + lw $16,24($sp) + ldc1 $f22,48($sp) + ldc1 $f20,40($sp) + j $31 + addiu $sp,$sp,56 + + .set macro + .set reorder + .end __start diff --git a/ld/testsuite/ld-mips-elf/mips16-intermix-2.s b/ld/testsuite/ld-mips-elf/mips16-intermix-2.s new file mode 100644 index 0000000..472f0c9 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/mips16-intermix-2.s @@ -0,0 +1,2631 @@ + .text + .align 2 + .globl m32_l + .set nomips16 + .ent m32_l +m32_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + move $2,$4 + + .set macro + .set reorder + .end m32_l + + .align 2 + .globl m16_l + .set mips16 + .ent m16_l +m16_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + j $31 + move $2,$4 + .set macro + .set reorder + + .end m16_l + + .align 2 + .set nomips16 + .ent m32_static_l +m32_static_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + move $2,$4 + + .set macro + .set reorder + .end m32_static_l + + .align 2 + .set mips16 + .ent m16_static_l +m16_static_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + j $31 + move $2,$4 + .set macro + .set reorder + + .end m16_static_l + + .align 2 + .set nomips16 + .ent m32_static1_l +m32_static1_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + move $2,$4 + + .set macro + .set reorder + .end m32_static1_l + + .align 2 + .set mips16 + .ent m16_static1_l +m16_static1_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + j $31 + move $2,$4 + .set macro + .set reorder + + .end m16_static1_l + + .align 2 + .set nomips16 + .ent m32_static32_l +m32_static32_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + move $2,$4 + + .set macro + .set reorder + .end m32_static32_l + + .align 2 + .set mips16 + .ent m16_static32_l +m16_static32_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + j $31 + move $2,$4 + .set macro + .set reorder + + .end m16_static32_l + + .align 2 + .set nomips16 + .ent m32_static16_l +m32_static16_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + move $2,$4 + + .set macro + .set reorder + .end m32_static16_l + + .align 2 + .set mips16 + .ent m16_static16_l +m16_static16_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + j $31 + move $2,$4 + .set macro + .set reorder + + .end m16_static16_l + + .align 2 + .globl m32_d + .set nomips16 + .ent m32_d +m32_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f12,$f12 + j $31 + mfc1 $2,$f12 + + .set macro + .set reorder + .end m32_d + + .align 2 + .globl m16_d + .set mips16 + .ent m16_d +m16_d: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + #jal __mips16_fixdfsi + restore 24,$31 + j $31 + .end m16_d + # Stub function for m16_d (double) + .set nomips16 + .section .mips16.fn.m16_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_d +__fn_stub_m16_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_d + .previous + + .align 2 + .set nomips16 + .ent m32_static_d +m32_static_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f12,$f12 + j $31 + mfc1 $2,$f12 + + .set macro + .set reorder + .end m32_static_d + + .align 2 + .set mips16 + .ent m16_static_d +m16_static_d: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + #jal __mips16_fixdfsi + restore 24,$31 + j $31 + .end m16_static_d + # Stub function for m16_static_d (double) + .set nomips16 + .section .mips16.fn.m16_static_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static_d +__fn_stub_m16_static_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static_d + .previous + + .align 2 + .set nomips16 + .ent m32_static1_d +m32_static1_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f12,$f12 + j $31 + mfc1 $2,$f12 + + .set macro + .set reorder + .end m32_static1_d + + .align 2 + .set mips16 + .ent m16_static1_d +m16_static1_d: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + #jal __mips16_fixdfsi + restore 24,$31 + j $31 + .end m16_static1_d + # Stub function for m16_static1_d (double) + .set nomips16 + .section .mips16.fn.m16_static1_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static1_d +__fn_stub_m16_static1_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static1_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static1_d + .previous + + .align 2 + .set nomips16 + .ent m32_static32_d +m32_static32_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f12,$f12 + j $31 + mfc1 $2,$f12 + + .set macro + .set reorder + .end m32_static32_d + + .align 2 + .set mips16 + .ent m16_static32_d +m16_static32_d: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + #jal __mips16_fixdfsi + restore 24,$31 + j $31 + .end m16_static32_d + # Stub function for m16_static32_d (double) + .set nomips16 + .section .mips16.fn.m16_static32_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static32_d +__fn_stub_m16_static32_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static32_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static32_d + .previous + + .align 2 + .set nomips16 + .ent m32_static16_d +m32_static16_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f12,$f12 + j $31 + mfc1 $2,$f12 + + .set macro + .set reorder + .end m32_static16_d + + .align 2 + .set mips16 + .ent m16_static16_d +m16_static16_d: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + #jal __mips16_fixdfsi + restore 24,$31 + j $31 + .end m16_static16_d + # Stub function for m16_static16_d (double) + .set nomips16 + .section .mips16.fn.m16_static16_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static16_d +__fn_stub_m16_static16_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static16_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static16_d + .previous + + .align 2 + .globl m32_ld + .set nomips16 + .ent m32_ld +m32_ld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $7,$f2 + mtc1 $6,$f3 + trunc.w.d $f0,$f2 + mfc1 $24,$f0 + j $31 + addu $2,$24,$4 + + .set macro + .set reorder + .end m32_ld + + .align 2 + .globl m16_ld + .set mips16 + .ent m16_ld +m16_ld: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + move $16,$4 + move $5,$7 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $4,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_ld + + .align 2 + .set nomips16 + .ent m32_static_ld +m32_static_ld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $7,$f2 + mtc1 $6,$f3 + trunc.w.d $f0,$f2 + mfc1 $24,$f0 + j $31 + addu $2,$24,$4 + + .set macro + .set reorder + .end m32_static_ld + + .align 2 + .set mips16 + .ent m16_static_ld +m16_static_ld: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + move $16,$4 + move $5,$7 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $4,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static_ld + + .align 2 + .set nomips16 + .ent m32_static1_ld +m32_static1_ld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $7,$f2 + mtc1 $6,$f3 + trunc.w.d $f0,$f2 + mfc1 $24,$f0 + j $31 + addu $2,$24,$4 + + .set macro + .set reorder + .end m32_static1_ld + + .align 2 + .set mips16 + .ent m16_static1_ld +m16_static1_ld: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + move $16,$4 + move $5,$7 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $4,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static1_ld + + .align 2 + .set nomips16 + .ent m32_static32_ld +m32_static32_ld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $7,$f2 + mtc1 $6,$f3 + trunc.w.d $f0,$f2 + mfc1 $24,$f0 + j $31 + addu $2,$24,$4 + + .set macro + .set reorder + .end m32_static32_ld + + .align 2 + .set mips16 + .ent m16_static32_ld +m16_static32_ld: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + move $16,$4 + move $5,$7 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $4,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static32_ld + + .align 2 + .set nomips16 + .ent m32_static16_ld +m32_static16_ld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $7,$f2 + mtc1 $6,$f3 + trunc.w.d $f0,$f2 + mfc1 $24,$f0 + j $31 + addu $2,$24,$4 + + .set macro + .set reorder + .end m32_static16_ld + + .align 2 + .set mips16 + .ent m16_static16_ld +m16_static16_ld: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + move $16,$4 + move $5,$7 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $4,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static16_ld + + .align 2 + .globl m32_dl + .set nomips16 + .ent m32_dl +m32_dl: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f0,$f12 + mfc1 $24,$f0 + j $31 + addu $2,$24,$6 + + .set macro + .set reorder + .end m32_dl + + .align 2 + .globl m16_dl + .set mips16 + .ent m16_dl +m16_dl: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $16,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_dl + # Stub function for m16_dl (double) + .set nomips16 + .section .mips16.fn.m16_dl,"ax",@progbits + .align 2 + .ent __fn_stub_m16_dl +__fn_stub_m16_dl: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_dl + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_dl + .previous + + .align 2 + .set nomips16 + .ent m32_static_dl +m32_static_dl: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f0,$f12 + mfc1 $24,$f0 + j $31 + addu $2,$24,$6 + + .set macro + .set reorder + .end m32_static_dl + + .align 2 + .set mips16 + .ent m16_static_dl +m16_static_dl: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $16,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static_dl + # Stub function for m16_static_dl (double) + .set nomips16 + .section .mips16.fn.m16_static_dl,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static_dl +__fn_stub_m16_static_dl: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static_dl + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static_dl + .previous + + .align 2 + .set nomips16 + .ent m32_static1_dl +m32_static1_dl: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f0,$f12 + mfc1 $24,$f0 + j $31 + addu $2,$24,$6 + + .set macro + .set reorder + .end m32_static1_dl + + .align 2 + .set mips16 + .ent m16_static1_dl +m16_static1_dl: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $16,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static1_dl + # Stub function for m16_static1_dl (double) + .set nomips16 + .section .mips16.fn.m16_static1_dl,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static1_dl +__fn_stub_m16_static1_dl: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static1_dl + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static1_dl + .previous + + .align 2 + .set nomips16 + .ent m32_static32_dl +m32_static32_dl: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f0,$f12 + mfc1 $24,$f0 + j $31 + addu $2,$24,$6 + + .set macro + .set reorder + .end m32_static32_dl + + .align 2 + .set mips16 + .ent m16_static32_dl +m16_static32_dl: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $16,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static32_dl + # Stub function for m16_static32_dl (double) + .set nomips16 + .section .mips16.fn.m16_static32_dl,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static32_dl +__fn_stub_m16_static32_dl: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static32_dl + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static32_dl + .previous + + .align 2 + .set nomips16 + .ent m32_static16_dl +m32_static16_dl: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f0,$f12 + mfc1 $24,$f0 + j $31 + addu $2,$24,$6 + + .set macro + .set reorder + .end m32_static16_dl + + .align 2 + .set mips16 + .ent m16_static16_dl +m16_static16_dl: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $16,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static16_dl + # Stub function for m16_static16_dl (double) + .set nomips16 + .section .mips16.fn.m16_static16_dl,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static16_dl +__fn_stub_m16_static16_dl: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static16_dl + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static16_dl + .previous + + .align 2 + .globl m32_dlld + .set nomips16 + .ent m32_dlld +m32_dlld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f1,$f12 + mfc1 $4,$f1 + addu $3,$4,$6 + addu $2,$3,$7 + ldc1 $f0,16($sp) + trunc.w.d $f2,$f0 + mfc1 $24,$f2 + j $31 + addu $2,$2,$24 + + .set macro + .set reorder + .end m32_dlld + + .align 2 + .globl m16_dlld + .set mips16 + .ent m16_dlld +m16_dlld: + .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 + .mask 0x80030000,-4 + .fmask 0x00000000,0 + save 32,$16,$17,$31 + move $16,$6 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $17,$7 + .set macro + .set reorder + + lw $5,52($sp) + lw $4,48($sp) + addu $16,$2,$16 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + addu $16,$17 + .set macro + .set reorder + + addu $2,$16,$2 + restore 32,$16,$17,$31 + j $31 + .end m16_dlld + # Stub function for m16_dlld (double) + .set nomips16 + .section .mips16.fn.m16_dlld,"ax",@progbits + .align 2 + .ent __fn_stub_m16_dlld +__fn_stub_m16_dlld: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_dlld + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_dlld + .previous + + .align 2 + .set nomips16 + .ent m32_static_dlld +m32_static_dlld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f1,$f12 + mfc1 $4,$f1 + addu $3,$4,$6 + addu $2,$3,$7 + ldc1 $f0,16($sp) + trunc.w.d $f2,$f0 + mfc1 $24,$f2 + j $31 + addu $2,$2,$24 + + .set macro + .set reorder + .end m32_static_dlld + + .align 2 + .set mips16 + .ent m16_static_dlld +m16_static_dlld: + .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 + .mask 0x80030000,-4 + .fmask 0x00000000,0 + save 32,$16,$17,$31 + move $16,$6 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $17,$7 + .set macro + .set reorder + + lw $5,52($sp) + lw $4,48($sp) + addu $16,$2,$16 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + addu $16,$17 + .set macro + .set reorder + + addu $2,$16,$2 + restore 32,$16,$17,$31 + j $31 + .end m16_static_dlld + # Stub function for m16_static_dlld (double) + .set nomips16 + .section .mips16.fn.m16_static_dlld,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static_dlld +__fn_stub_m16_static_dlld: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static_dlld + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static_dlld + .previous + + .align 2 + .set nomips16 + .ent m32_static1_dlld +m32_static1_dlld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f1,$f12 + mfc1 $4,$f1 + addu $3,$4,$6 + addu $2,$3,$7 + ldc1 $f0,16($sp) + trunc.w.d $f2,$f0 + mfc1 $24,$f2 + j $31 + addu $2,$2,$24 + + .set macro + .set reorder + .end m32_static1_dlld + + .align 2 + .set mips16 + .ent m16_static1_dlld +m16_static1_dlld: + .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 + .mask 0x80030000,-4 + .fmask 0x00000000,0 + save 32,$16,$17,$31 + move $16,$6 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $17,$7 + .set macro + .set reorder + + lw $5,52($sp) + lw $4,48($sp) + addu $16,$2,$16 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + addu $16,$17 + .set macro + .set reorder + + addu $2,$16,$2 + restore 32,$16,$17,$31 + j $31 + .end m16_static1_dlld + # Stub function for m16_static1_dlld (double) + .set nomips16 + .section .mips16.fn.m16_static1_dlld,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static1_dlld +__fn_stub_m16_static1_dlld: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static1_dlld + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static1_dlld + .previous + + .align 2 + .set nomips16 + .ent m32_static32_dlld +m32_static32_dlld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f1,$f12 + mfc1 $4,$f1 + addu $3,$4,$6 + addu $2,$3,$7 + ldc1 $f0,16($sp) + trunc.w.d $f2,$f0 + mfc1 $24,$f2 + j $31 + addu $2,$2,$24 + + .set macro + .set reorder + .end m32_static32_dlld + + .align 2 + .set mips16 + .ent m16_static32_dlld +m16_static32_dlld: + .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 + .mask 0x80030000,-4 + .fmask 0x00000000,0 + save 32,$16,$17,$31 + move $16,$6 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $17,$7 + .set macro + .set reorder + + lw $5,52($sp) + lw $4,48($sp) + addu $16,$2,$16 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + addu $16,$17 + .set macro + .set reorder + + addu $2,$16,$2 + restore 32,$16,$17,$31 + j $31 + .end m16_static32_dlld + # Stub function for m16_static32_dlld (double) + .set nomips16 + .section .mips16.fn.m16_static32_dlld,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static32_dlld +__fn_stub_m16_static32_dlld: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static32_dlld + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static32_dlld + .previous + + .align 2 + .set nomips16 + .ent m32_static16_dlld +m32_static16_dlld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f1,$f12 + mfc1 $4,$f1 + addu $3,$4,$6 + addu $2,$3,$7 + ldc1 $f0,16($sp) + trunc.w.d $f2,$f0 + mfc1 $24,$f2 + j $31 + addu $2,$2,$24 + + .set macro + .set reorder + .end m32_static16_dlld + + .align 2 + .set mips16 + .ent m16_static16_dlld +m16_static16_dlld: + .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 + .mask 0x80030000,-4 + .fmask 0x00000000,0 + save 32,$16,$17,$31 + move $16,$6 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + move $17,$7 + .set macro + .set reorder + + lw $5,52($sp) + lw $4,48($sp) + addu $16,$2,$16 + .set noreorder + .set nomacro + #jal __mips16_fixdfsi + addu $16,$17 + .set macro + .set reorder + + addu $2,$16,$2 + restore 32,$16,$17,$31 + j $31 + .end m16_static16_dlld + # Stub function for m16_static16_dlld (double) + .set nomips16 + .section .mips16.fn.m16_static16_dlld,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static16_dlld +__fn_stub_m16_static16_dlld: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static16_dlld + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static16_dlld + .previous + + .align 2 + .globl m32_d_l + .set nomips16 + .ent m32_d_l +m32_d_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $4,$f2 + j $31 + cvt.d.w $f0,$f2 + + .set macro + .set reorder + .end m32_d_l + + .align 2 + .globl m16_d_l + .set mips16 + .ent m16_d_l +m16_d_l: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + #jal __mips16_floatsidf + #jal __mips16_ret_df + restore 24,$31 + j $31 + .end m16_d_l + + .align 2 + .set nomips16 + .ent m32_static_d_l +m32_static_d_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $4,$f2 + j $31 + cvt.d.w $f0,$f2 + + .set macro + .set reorder + .end m32_static_d_l + + .align 2 + .set mips16 + .ent m16_static_d_l +m16_static_d_l: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + #jal __mips16_floatsidf + #jal __mips16_ret_df + restore 24,$31 + j $31 + .end m16_static_d_l + + .align 2 + .set nomips16 + .ent m32_static1_d_l +m32_static1_d_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $4,$f2 + j $31 + cvt.d.w $f0,$f2 + + .set macro + .set reorder + .end m32_static1_d_l + + .align 2 + .set mips16 + .ent m16_static1_d_l +m16_static1_d_l: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + #jal __mips16_floatsidf + #jal __mips16_ret_df + restore 24,$31 + j $31 + .end m16_static1_d_l + + .align 2 + .set nomips16 + .ent m32_static32_d_l +m32_static32_d_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $4,$f2 + j $31 + cvt.d.w $f0,$f2 + + .set macro + .set reorder + .end m32_static32_d_l + + .align 2 + .set mips16 + .ent m16_static32_d_l +m16_static32_d_l: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + #jal __mips16_floatsidf + #jal __mips16_ret_df + restore 24,$31 + j $31 + .end m16_static32_d_l + + .align 2 + .set nomips16 + .ent m32_static16_d_l +m32_static16_d_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $4,$f2 + j $31 + cvt.d.w $f0,$f2 + + .set macro + .set reorder + .end m32_static16_d_l + + .align 2 + .set mips16 + .ent m16_static16_d_l +m16_static16_d_l: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + #jal __mips16_floatsidf + #jal __mips16_ret_df + restore 24,$31 + j $31 + .end m16_static16_d_l + + .align 2 + .globl m32_d_d + .set nomips16 + .ent m32_d_d +m32_d_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + mov.d $f0,$f12 + + .set macro + .set reorder + .end m32_d_d + + .align 2 + .globl m16_d_d + .set mips16 + .ent m16_d_d +m16_d_d: + .frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 8,$31 + move $3,$5 + .set noreorder + .set nomacro + #jal __mips16_ret_df + move $2,$4 + .set macro + .set reorder + + restore 8,$31 + j $31 + .end m16_d_d + # Stub function for m16_d_d (double) + .set nomips16 + .section .mips16.fn.m16_d_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_d_d +__fn_stub_m16_d_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_d_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_d_d + .previous + + .align 2 + .set nomips16 + .ent m32_static_d_d +m32_static_d_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + mov.d $f0,$f12 + + .set macro + .set reorder + .end m32_static_d_d + + .align 2 + .set mips16 + .ent m16_static_d_d +m16_static_d_d: + .frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 8,$31 + move $3,$5 + .set noreorder + .set nomacro + #jal __mips16_ret_df + move $2,$4 + .set macro + .set reorder + + restore 8,$31 + j $31 + .end m16_static_d_d + # Stub function for m16_static_d_d (double) + .set nomips16 + .section .mips16.fn.m16_static_d_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static_d_d +__fn_stub_m16_static_d_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static_d_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static_d_d + .previous + + .align 2 + .set nomips16 + .ent m32_static1_d_d +m32_static1_d_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + mov.d $f0,$f12 + + .set macro + .set reorder + .end m32_static1_d_d + + .align 2 + .set mips16 + .ent m16_static1_d_d +m16_static1_d_d: + .frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 8,$31 + move $3,$5 + .set noreorder + .set nomacro + #jal __mips16_ret_df + move $2,$4 + .set macro + .set reorder + + restore 8,$31 + j $31 + .end m16_static1_d_d + # Stub function for m16_static1_d_d (double) + .set nomips16 + .section .mips16.fn.m16_static1_d_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static1_d_d +__fn_stub_m16_static1_d_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static1_d_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static1_d_d + .previous + + .align 2 + .set nomips16 + .ent m32_static32_d_d +m32_static32_d_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + mov.d $f0,$f12 + + .set macro + .set reorder + .end m32_static32_d_d + + .align 2 + .set mips16 + .ent m16_static32_d_d +m16_static32_d_d: + .frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 8,$31 + move $3,$5 + .set noreorder + .set nomacro + #jal __mips16_ret_df + move $2,$4 + .set macro + .set reorder + + restore 8,$31 + j $31 + .end m16_static32_d_d + # Stub function for m16_static32_d_d (double) + .set nomips16 + .section .mips16.fn.m16_static32_d_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static32_d_d +__fn_stub_m16_static32_d_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static32_d_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static32_d_d + .previous + + .align 2 + .set nomips16 + .ent m32_static16_d_d +m32_static16_d_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + mov.d $f0,$f12 + + .set macro + .set reorder + .end m32_static16_d_d + + .align 2 + .set mips16 + .ent m16_static16_d_d +m16_static16_d_d: + .frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 8,$31 + move $3,$5 + .set noreorder + .set nomacro + #jal __mips16_ret_df + move $2,$4 + .set macro + .set reorder + + restore 8,$31 + j $31 + .end m16_static16_d_d + # Stub function for m16_static16_d_d (double) + .set nomips16 + .section .mips16.fn.m16_static16_d_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static16_d_d +__fn_stub_m16_static16_d_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static16_d_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static16_d_d + .previous + + .align 2 + .globl f32 + .set nomips16 + .ent f32 +f32: + .frame $sp,64,$31 # vars= 0, regs= 3/3, args= 24, gp= 0 + .mask 0x80030000,-32 + .fmask 0x03f00000,-8 + .set noreorder + .set nomacro + + addiu $sp,$sp,-64 + sw $17,28($sp) + move $17,$4 + sw $31,32($sp) + sdc1 $f24,56($sp) + sw $16,24($sp) + sdc1 $f22,48($sp) + sdc1 $f20,40($sp) + mtc1 $7,$f22 + jal m32_static1_l + mtc1 $6,$f23 + + move $4,$17 + jal m16_static1_l + move $16,$2 + + addu $16,$16,$2 + jal m32_static1_d + mov.d $f12,$f22 + + addu $16,$16,$2 + jal m16_static1_d + mov.d $f12,$f22 + + move $4,$17 + mfc1 $7,$f22 + mfc1 $6,$f23 + jal m32_static1_ld + addu $16,$16,$2 + + move $4,$17 + mfc1 $7,$f22 + mfc1 $6,$f23 + jal m16_static1_ld + addu $16,$16,$2 + + move $6,$17 + mov.d $f12,$f22 + jal m32_static1_dl + addu $16,$16,$2 + + move $6,$17 + mov.d $f12,$f22 + jal m16_static1_dl + addu $16,$16,$2 + + move $6,$17 + move $7,$17 + sdc1 $f22,16($sp) + mov.d $f12,$f22 + jal m32_static1_dlld + addu $16,$16,$2 + + move $6,$17 + move $7,$17 + mov.d $f12,$f22 + sdc1 $f22,16($sp) + jal m16_static1_dlld + addu $16,$16,$2 + + move $4,$17 + jal m32_static1_d_l + addu $16,$16,$2 + + move $4,$17 + jal m16_static1_d_l + mov.d $f20,$f0 + + add.d $f20,$f20,$f0 + jal m32_static1_d_d + mov.d $f12,$f22 + + add.d $f20,$f20,$f0 + jal m16_static1_d_d + mov.d $f12,$f22 + + move $4,$17 + jal m32_static32_l + add.d $f20,$f20,$f0 + + move $4,$17 + jal m16_static32_l + addu $16,$16,$2 + + addu $16,$16,$2 + jal m32_static32_d + mov.d $f12,$f22 + + addu $16,$16,$2 + jal m16_static32_d + mov.d $f12,$f22 + + move $4,$17 + mfc1 $7,$f22 + mfc1 $6,$f23 + jal m32_static32_ld + addu $16,$16,$2 + + move $4,$17 + mfc1 $7,$f22 + mfc1 $6,$f23 + jal m16_static32_ld + addu $16,$16,$2 + + move $6,$17 + mov.d $f12,$f22 + jal m32_static32_dl + addu $16,$16,$2 + + move $6,$17 + mov.d $f12,$f22 + jal m16_static32_dl + addu $16,$16,$2 + + move $6,$17 + move $7,$17 + sdc1 $f22,16($sp) + mov.d $f12,$f22 + jal m32_static32_dlld + addu $16,$16,$2 + + move $6,$17 + move $7,$17 + mov.d $f12,$f22 + sdc1 $f22,16($sp) + jal m16_static32_dlld + addu $16,$16,$2 + + move $4,$17 + jal m32_static32_d_l + addu $16,$16,$2 + + move $4,$17 + jal m16_static32_d_l + add.d $f20,$f20,$f0 + + add.d $f20,$f20,$f0 + jal m32_static32_d_d + mov.d $f12,$f22 + + mtc1 $16,$f24 + add.d $f20,$f20,$f0 + jal m16_static32_d_d + mov.d $f12,$f22 + + lw $31,32($sp) + lw $17,28($sp) + lw $16,24($sp) + add.d $f20,$f20,$f0 + ldc1 $f22,48($sp) + cvt.d.w $f0,$f24 + ldc1 $f24,56($sp) + add.d $f0,$f0,$f20 + ldc1 $f20,40($sp) + j $31 + addiu $sp,$sp,64 + + .set macro + .set reorder + .end f32 + + # Stub function to call m32_static1_d (double) + .set nomips16 + .section .mips16.call.m32_static1_d,"ax",@progbits + .align 2 + .ent __call_stub_m32_static1_d +__call_stub_m32_static1_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m32_static1_d + jr $1 + .set at + nop + .set reorder + .end __call_stub_m32_static1_d + .previous + + # Stub function to call m16_static1_d (double) + .set nomips16 + .section .mips16.call.m16_static1_d,"ax",@progbits + .align 2 + .ent __call_stub_m16_static1_d +__call_stub_m16_static1_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m16_static1_d + jr $1 + .set at + nop + .set reorder + .end __call_stub_m16_static1_d + .previous + + # Stub function to call m32_static1_dl (double) + .set nomips16 + .section .mips16.call.m32_static1_dl,"ax",@progbits + .align 2 + .ent __call_stub_m32_static1_dl +__call_stub_m32_static1_dl: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m32_static1_dl + jr $1 + .set at + nop + .set reorder + .end __call_stub_m32_static1_dl + .previous + + # Stub function to call m16_static1_dl (double) + .set nomips16 + .section .mips16.call.m16_static1_dl,"ax",@progbits + .align 2 + .ent __call_stub_m16_static1_dl +__call_stub_m16_static1_dl: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m16_static1_dl + jr $1 + .set at + nop + .set reorder + .end __call_stub_m16_static1_dl + .previous + + # Stub function to call m32_static1_dlld (double) + .set nomips16 + .section .mips16.call.m32_static1_dlld,"ax",@progbits + .align 2 + .ent __call_stub_m32_static1_dlld +__call_stub_m32_static1_dlld: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m32_static1_dlld + jr $1 + .set at + nop + .set reorder + .end __call_stub_m32_static1_dlld + .previous + + # Stub function to call m16_static1_dlld (double) + .set nomips16 + .section .mips16.call.m16_static1_dlld,"ax",@progbits + .align 2 + .ent __call_stub_m16_static1_dlld +__call_stub_m16_static1_dlld: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m16_static1_dlld + jr $1 + .set at + nop + .set reorder + .end __call_stub_m16_static1_dlld + .previous + + # Stub function to call double m32_static1_d_l () + .set nomips16 + .section .mips16.call.fp.m32_static1_d_l,"ax",@progbits + .align 2 + .ent __call_stub_fp_m32_static1_d_l +__call_stub_fp_m32_static1_d_l: + .set noreorder + move $18,$31 + jal m32_static1_d_l + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m32_static1_d_l + .previous + + # Stub function to call double m16_static1_d_l () + .set nomips16 + .section .mips16.call.fp.m16_static1_d_l,"ax",@progbits + .align 2 + .ent __call_stub_fp_m16_static1_d_l +__call_stub_fp_m16_static1_d_l: + .set noreorder + move $18,$31 + jal m16_static1_d_l + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m16_static1_d_l + .previous + + # Stub function to call double m32_static1_d_d (double) + .set nomips16 + .section .mips16.call.fp.m32_static1_d_d,"ax",@progbits + .align 2 + .ent __call_stub_fp_m32_static1_d_d +__call_stub_fp_m32_static1_d_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + move $18,$31 + jal m32_static1_d_d + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m32_static1_d_d + .previous + + # Stub function to call double m16_static1_d_d (double) + .set nomips16 + .section .mips16.call.fp.m16_static1_d_d,"ax",@progbits + .align 2 + .ent __call_stub_fp_m16_static1_d_d +__call_stub_fp_m16_static1_d_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + move $18,$31 + jal m16_static1_d_d + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m16_static1_d_d + .previous + + # Stub function to call m32_static16_d (double) + .set nomips16 + .section .mips16.call.m32_static16_d,"ax",@progbits + .align 2 + .ent __call_stub_m32_static16_d +__call_stub_m32_static16_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m32_static16_d + jr $1 + .set at + nop + .set reorder + .end __call_stub_m32_static16_d + .previous + + # Stub function to call m16_static16_d (double) + .set nomips16 + .section .mips16.call.m16_static16_d,"ax",@progbits + .align 2 + .ent __call_stub_m16_static16_d +__call_stub_m16_static16_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m16_static16_d + jr $1 + .set at + nop + .set reorder + .end __call_stub_m16_static16_d + .previous + + # Stub function to call m32_static16_dl (double) + .set nomips16 + .section .mips16.call.m32_static16_dl,"ax",@progbits + .align 2 + .ent __call_stub_m32_static16_dl +__call_stub_m32_static16_dl: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m32_static16_dl + jr $1 + .set at + nop + .set reorder + .end __call_stub_m32_static16_dl + .previous + + # Stub function to call m16_static16_dl (double) + .set nomips16 + .section .mips16.call.m16_static16_dl,"ax",@progbits + .align 2 + .ent __call_stub_m16_static16_dl +__call_stub_m16_static16_dl: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m16_static16_dl + jr $1 + .set at + nop + .set reorder + .end __call_stub_m16_static16_dl + .previous + + # Stub function to call m32_static16_dlld (double) + .set nomips16 + .section .mips16.call.m32_static16_dlld,"ax",@progbits + .align 2 + .ent __call_stub_m32_static16_dlld +__call_stub_m32_static16_dlld: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m32_static16_dlld + jr $1 + .set at + nop + .set reorder + .end __call_stub_m32_static16_dlld + .previous + + # Stub function to call m16_static16_dlld (double) + .set nomips16 + .section .mips16.call.m16_static16_dlld,"ax",@progbits + .align 2 + .ent __call_stub_m16_static16_dlld +__call_stub_m16_static16_dlld: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m16_static16_dlld + jr $1 + .set at + nop + .set reorder + .end __call_stub_m16_static16_dlld + .previous + + # Stub function to call double m32_static16_d_l () + .set nomips16 + .section .mips16.call.fp.m32_static16_d_l,"ax",@progbits + .align 2 + .ent __call_stub_fp_m32_static16_d_l +__call_stub_fp_m32_static16_d_l: + .set noreorder + move $18,$31 + jal m32_static16_d_l + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m32_static16_d_l + .previous + + # Stub function to call double m16_static16_d_l () + .set nomips16 + .section .mips16.call.fp.m16_static16_d_l,"ax",@progbits + .align 2 + .ent __call_stub_fp_m16_static16_d_l +__call_stub_fp_m16_static16_d_l: + .set noreorder + move $18,$31 + jal m16_static16_d_l + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m16_static16_d_l + .previous + + # Stub function to call double m32_static16_d_d (double) + .set nomips16 + .section .mips16.call.fp.m32_static16_d_d,"ax",@progbits + .align 2 + .ent __call_stub_fp_m32_static16_d_d +__call_stub_fp_m32_static16_d_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + move $18,$31 + jal m32_static16_d_d + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m32_static16_d_d + .previous + + # Stub function to call double m16_static16_d_d (double) + .set nomips16 + .section .mips16.call.fp.m16_static16_d_d,"ax",@progbits + .align 2 + .ent __call_stub_fp_m16_static16_d_d +__call_stub_fp_m16_static16_d_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + move $18,$31 + jal m16_static16_d_d + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m16_static16_d_d + .previous + + .align 2 + .globl f16 + .set mips16 + .ent f16 +f16: + .frame $sp,104,$31 # vars= 64, regs= 4/0, args= 24, gp= 0 + .mask 0x80070000,-4 + .fmask 0x00000000,0 + save 104,$16,$17,$18,$31 + move $17,$4 + sw $7,116($sp) + .set noreorder + .set nomacro + jal m32_static1_l + sw $6,112($sp) + .set macro + .set reorder + + move $4,$17 + .set noreorder + .set nomacro + jal m16_static1_l + move $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + .set noreorder + .set nomacro + jal m32_static1_d + addu $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + .set noreorder + .set nomacro + jal m16_static1_d + addu $16,$2 + .set macro + .set reorder + + lw $7,116($sp) + lw $6,112($sp) + move $4,$17 + .set noreorder + .set nomacro + jal m32_static1_ld + addu $16,$2 + .set macro + .set reorder + + lw $7,116($sp) + lw $6,112($sp) + move $4,$17 + .set noreorder + .set nomacro + jal m16_static1_ld + addu $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + move $6,$17 + .set noreorder + .set nomacro + jal m32_static1_dl + addu $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + move $6,$17 + .set noreorder + .set nomacro + jal m16_static1_dl + addu $16,$2 + .set macro + .set reorder + + lw $3,116($sp) + lw $6,112($sp) + sw $3,20($sp) + move $5,$3 + sw $6,16($sp) + move $4,$6 + move $7,$17 + move $6,$17 + .set noreorder + .set nomacro + jal m32_static1_dlld + addu $16,$2 + .set macro + .set reorder + + addu $16,$2 + lw $7,112($sp) + lw $2,116($sp) + move $6,$17 + move $5,$2 + sw $7,16($sp) + move $4,$7 + sw $2,20($sp) + .set noreorder + .set nomacro + jal m16_static1_dlld + move $7,$17 + .set macro + .set reorder + + move $4,$17 + .set noreorder + .set nomacro + jal m32_static1_d_l + addu $16,$2 + .set macro + .set reorder + + move $4,$17 + sw $3,28($sp) + .set noreorder + .set nomacro + jal m16_static1_d_l + sw $2,24($sp) + .set macro + .set reorder + + lw $5,28($sp) + lw $4,24($sp) + move $7,$3 + .set noreorder + .set nomacro + #jal __mips16_adddf3 + move $6,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + sw $3,36($sp) + .set noreorder + .set nomacro + jal m32_static1_d_d + sw $2,32($sp) + .set macro + .set reorder + + lw $5,36($sp) + lw $4,32($sp) + move $7,$3 + .set noreorder + .set nomacro + #jal __mips16_adddf3 + move $6,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + sw $3,44($sp) + .set noreorder + .set nomacro + jal m16_static1_d_d + sw $2,40($sp) + .set macro + .set reorder + + lw $5,44($sp) + lw $4,40($sp) + move $7,$3 + .set noreorder + .set nomacro + #jal __mips16_adddf3 + move $6,$2 + .set macro + .set reorder + + move $4,$17 + sw $3,52($sp) + .set noreorder + .set nomacro + jal m32_static16_l + sw $2,48($sp) + .set macro + .set reorder + + move $4,$17 + .set noreorder + .set nomacro + jal m16_static16_l + addu $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + .set noreorder + .set nomacro + jal m32_static16_d + addu $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + .set noreorder + .set nomacro + jal m16_static16_d + addu $16,$2 + .set macro + .set reorder + + lw $7,116($sp) + lw $6,112($sp) + move $4,$17 + .set noreorder + .set nomacro + jal m32_static16_ld + addu $16,$2 + .set macro + .set reorder + + lw $7,116($sp) + lw $6,112($sp) + move $4,$17 + .set noreorder + .set nomacro + jal m16_static16_ld + addu $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + move $6,$17 + .set noreorder + .set nomacro + jal m32_static16_dl + addu $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + move $6,$17 + .set noreorder + .set nomacro + jal m16_static16_dl + addu $16,$2 + .set macro + .set reorder + + lw $4,116($sp) + lw $6,112($sp) + sw $4,20($sp) + sw $6,16($sp) + move $5,$4 + move $7,$17 + move $4,$6 + move $6,$17 + .set noreorder + .set nomacro + jal m32_static16_dlld + addu $16,$2 + .set macro + .set reorder + + addu $16,$2 + lw $3,116($sp) + lw $2,112($sp) + move $6,$17 + move $7,$17 + sw $3,20($sp) + move $5,$3 + sw $2,16($sp) + .set noreorder + .set nomacro + jal m16_static16_dlld + move $4,$2 + .set macro + .set reorder + + move $4,$17 + .set noreorder + .set nomacro + jal m32_static16_d_l + addu $16,$2 + .set macro + .set reorder + + lw $5,52($sp) + lw $4,48($sp) + move $7,$3 + .set noreorder + .set nomacro + #jal __mips16_adddf3 + move $6,$2 + .set macro + .set reorder + + move $4,$17 + sw $3,60($sp) + .set noreorder + .set nomacro + jal m16_static16_d_l + sw $2,56($sp) + .set macro + .set reorder + + lw $5,60($sp) + lw $4,56($sp) + move $7,$3 + .set noreorder + .set nomacro + #jal __mips16_adddf3 + move $6,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + sw $3,68($sp) + .set noreorder + .set nomacro + jal m32_static16_d_d + sw $2,64($sp) + .set macro + .set reorder + + lw $5,68($sp) + lw $4,64($sp) + move $7,$3 + .set noreorder + .set nomacro + #jal __mips16_adddf3 + move $6,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + sw $3,76($sp) + .set noreorder + .set nomacro + jal m16_static16_d_d + sw $2,72($sp) + .set macro + .set reorder + + lw $5,76($sp) + lw $4,72($sp) + move $7,$3 + .set noreorder + .set nomacro + #jal __mips16_adddf3 + move $6,$2 + .set macro + .set reorder + + move $4,$16 + sw $3,84($sp) + .set noreorder + .set nomacro + #jal __mips16_floatsidf + sw $2,80($sp) + .set macro + .set reorder + + lw $7,84($sp) + lw $6,80($sp) + move $5,$3 + .set noreorder + .set nomacro + #jal __mips16_adddf3 + move $4,$2 + .set macro + .set reorder + + #jal __mips16_ret_df + restore 104,$16,$17,$18,$31 + j $31 + .end f16 diff --git a/ld/testsuite/ld-mips-elf/mips16-intermix.d b/ld/testsuite/ld-mips-elf/mips16-intermix.d new file mode 100644 index 0000000..5c6ee68 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/mips16-intermix.d @@ -0,0 +1,132 @@ + +.*: +file format elf.*mips + +SYMBOL TABLE: +#... +.* l F .text 0+[0-9a-f]+ m32_static_l +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static_l +.* l F .text 0+[0-9a-f]+ m32_static1_l +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static1_l +.* l F .text 0+[0-9a-f]+ m32_static32_l +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static32_l +.* l F .text 0+[0-9a-f]+ m32_static16_l +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static16_l +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_d +.* l F .text 0+[0-9a-f]+ m32_static_d +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static_d +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static_d +.* l F .text 0+[0-9a-f]+ m32_static1_d +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static1_d +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static1_d +.* l F .text 0+[0-9a-f]+ m32_static32_d +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static32_d +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static32_d +.* l F .text 0+[0-9a-f]+ m32_static16_d +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static16_d +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static16_d +.* l F .text 0+[0-9a-f]+ m32_static_ld +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static_ld +.* l F .text 0+[0-9a-f]+ m32_static1_ld +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static1_ld +.* l F .text 0+[0-9a-f]+ m32_static32_ld +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static32_ld +.* l F .text 0+[0-9a-f]+ m32_static16_ld +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static16_ld +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_dl +.* l F .text 0+[0-9a-f]+ m32_static_dl +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static_dl +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static_dl +.* l F .text 0+[0-9a-f]+ m32_static1_dl +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static1_dl +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static1_dl +.* l F .text 0+[0-9a-f]+ m32_static32_dl +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static32_dl +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static32_dl +.* l F .text 0+[0-9a-f]+ m32_static16_dl +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static16_dl +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static16_dl +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_dlld +.* l F .text 0+[0-9a-f]+ m32_static_dlld +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static_dlld +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static_dlld +.* l F .text 0+[0-9a-f]+ m32_static1_dlld +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static1_dlld +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static1_dlld +.* l F .text 0+[0-9a-f]+ m32_static32_dlld +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static32_dlld +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static32_dlld +.* l F .text 0+[0-9a-f]+ m32_static16_dlld +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static16_dlld +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static16_dlld +.* l F .text 0+[0-9a-f]+ m32_static_d_l +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static_d_l +.* l F .text 0+[0-9a-f]+ m32_static1_d_l +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static1_d_l +.* l F .text 0+[0-9a-f]+ m32_static32_d_l +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static32_d_l +.* l F .text 0+[0-9a-f]+ m32_static16_d_l +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static16_d_l +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_d_d +.* l F .text 0+[0-9a-f]+ m32_static_d_d +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static_d_d +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static_d_d +.* l F .text 0+[0-9a-f]+ m32_static1_d_d +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static1_d_d +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static1_d_d +.* l F .text 0+[0-9a-f]+ m32_static32_d_d +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static32_d_d +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static32_d_d +.* l F .text 0+[0-9a-f]+ m32_static16_d_d +.* l F .text 0+[0-9a-f]+ 0xf0 m16_static16_d_d +.* l F .text 0+[0-9a-f]+ __fn_stub_m16_static16_d_d +#... +.* l F .text 0+[0-9a-f]+ __call_stub_m32_static1_d +.* l F .text 0+[0-9a-f]+ __call_stub_m16_static1_d +.* l F .text 0+[0-9a-f]+ __call_stub_m32_static1_dl +.* l F .text 0+[0-9a-f]+ __call_stub_m16_static1_dl +.* l F .text 0+[0-9a-f]+ __call_stub_m32_static1_dlld +.* l F .text 0+[0-9a-f]+ __call_stub_m16_static1_dlld +.* l F .text 0+[0-9a-f]+ __call_stub_fp_m32_static1_d_l +.* l F .text 0+[0-9a-f]+ __call_stub_fp_m16_static1_d_l +.* l F .text 0+[0-9a-f]+ __call_stub_fp_m32_static1_d_d +.* l F .text 0+[0-9a-f]+ __call_stub_fp_m16_static1_d_d +.* l F .text 0+[0-9a-f]+ __call_stub_m32_static16_d +.* l F .text 0+[0-9a-f]+ __call_stub_m16_static16_d +.* l F .text 0+[0-9a-f]+ __call_stub_m32_static16_dl +.* l F .text 0+[0-9a-f]+ __call_stub_m16_static16_dl +.* l F .text 0+[0-9a-f]+ __call_stub_m32_static16_dlld +.* l F .text 0+[0-9a-f]+ __call_stub_m16_static16_dlld +.* l F .text 0+[0-9a-f]+ __call_stub_fp_m32_static16_d_l +.* l F .text 0+[0-9a-f]+ __call_stub_fp_m16_static16_d_l +.* l F .text 0+[0-9a-f]+ __call_stub_fp_m32_static16_d_d +.* l F .text 0+[0-9a-f]+ __call_stub_fp_m16_static16_d_d +#... +.* g F .text 0+[0-9a-f]+ m32_ld +#... +.* g F .text 0+[0-9a-f]+ m32_d_l +.* g F .text 0+[0-9a-f]+ 0xf0 m16_d_d +.* g F .text 0+[0-9a-f]+ 0xf0 m16_d +#... +.* g F .text 0+[0-9a-f]+ 0xf0 f16 +#... +.* g F .text 0+[0-9a-f]+ m32_d +#... +.* g F .text 0+[0-9a-f]+ 0xf0 m16_dl +#... +.* g F .text 0+[0-9a-f]+ f32 +#... +.* g F .text 0+[0-9a-f]+ 0xf0 m16_l +#... +.* g F .text 0+[0-9a-f]+ 0xf0 m16_ld +#... +.* g F .text 0+[0-9a-f]+ 0xf0 m16_dlld +.* g F .text 0+[0-9a-f]+ m32_d_d +#... +.* g F .text 0+[0-9a-f]+ m32_dl +#... +.* g F .text 0+[0-9a-f]+ m32_dlld +#... +.* g F .text 0+[0-9a-f]+ 0xf0 m16_d_l +#... +.* g F .text 0+[0-9a-f]+ m32_l +#pass |