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| author | Jan Beulich <jbeulich@suse.com> | 2023-09-01 12:26:46 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2023-09-01 12:26:46 +0200 |
| commit | f438659a6fb6cc4e388aac327c37362508f6a2c9 (patch) | |
| tree | 02a51dcd7f37d9c37f6949e1370766b505efdb84 /ld | |
| parent | be3bed0696aa3beea2c9d539e08743f14bbe1db1 (diff) | |
| download | gdb-f438659a6fb6cc4e388aac327c37362508f6a2c9.zip gdb-f438659a6fb6cc4e388aac327c37362508f6a2c9.tar.gz gdb-f438659a6fb6cc4e388aac327c37362508f6a2c9.tar.bz2 | |
RISC-V: move various alias entries
For disassembly to only use spec-mandated aliases, respective non-alias
entries need to come ahead of their alias ones. Since identical
mnemonics need to stay together, whole groups are moved up where
necessary.
This partly reverts 839189bc932e ("RISC-V: re-arrange opcode table for
consistent alias handling"), but then also goes beyond a plain revert.
Reviewed-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'ld')
| -rw-r--r-- | ld/testsuite/ld-riscv-elf/ifunc-plt-01.d | 2 | ||||
| -rw-r--r-- | ld/testsuite/ld-riscv-elf/ifunc-plt-02.d | 2 | ||||
| -rw-r--r-- | ld/testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d | 2 | ||||
| -rw-r--r-- | ld/testsuite/ld-riscv-elf/pcgp-relax-02.d | 4 | ||||
| -rw-r--r-- | ld/testsuite/ld-riscv-elf/relax-max-align-gp.d | 2 | ||||
| -rw-r--r-- | ld/testsuite/ld-riscv-elf/weakref32.d | 4 | ||||
| -rw-r--r-- | ld/testsuite/ld-riscv-elf/weakref64.d | 4 |
7 files changed, 10 insertions, 10 deletions
diff --git a/ld/testsuite/ld-riscv-elf/ifunc-plt-01.d b/ld/testsuite/ld-riscv-elf/ifunc-plt-01.d index 9c5b7cf..bed9fe6 100644 --- a/ld/testsuite/ld-riscv-elf/ifunc-plt-01.d +++ b/ld/testsuite/ld-riscv-elf/ifunc-plt-01.d @@ -11,7 +11,7 @@ Disassembly of section .text: .*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.* .*:[ ]+[0-9a-f]+[ ]+(lw|ld)[ ]+.*<(_GLOBAL_OFFSET_TABLE_.*|__DATA_BEGIN__.*|.*)> .*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.* -.*:[ ]+[0-9a-f]+[ ]+addi?[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)> +.*:[ ]+[0-9a-f]+[ ]+addi[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)> .*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.* .*:[ ]+[0-9a-f]+[ ]+jalr[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)> .*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.* diff --git a/ld/testsuite/ld-riscv-elf/ifunc-plt-02.d b/ld/testsuite/ld-riscv-elf/ifunc-plt-02.d index 4395781..b8638b9 100644 --- a/ld/testsuite/ld-riscv-elf/ifunc-plt-02.d +++ b/ld/testsuite/ld-riscv-elf/ifunc-plt-02.d @@ -13,7 +13,7 @@ Disassembly of section .text: .*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.* .*:[ ]+[0-9a-f]+[ ]+(lw|ld)[ ]+.*<(__DATA_BEGIN__.*|.*)> .*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.* -.*:[ ]+[0-9a-f]+[ ]+addi?[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)> +.*:[ ]+[0-9a-f]+[ ]+addi[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)> .*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.* .*:[ ]+[0-9a-f]+[ ]+jalr[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)> .*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.* diff --git a/ld/testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d b/ld/testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d index c020de9..bc947e3 100644 --- a/ld/testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d +++ b/ld/testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d @@ -9,7 +9,7 @@ Disassembly of section .text: #... 0+[0-9a-f]+ <bar>: .*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.* -.*:[ ]+[0-9a-f]+[ ]+addi?[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)> +.*:[ ]+[0-9a-f]+[ ]+addi[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)> .*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.* .*:[ ]+[0-9a-f]+[ ]+(lw|ld)[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)> #... diff --git a/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d b/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d index 055f03e..984d457 100644 --- a/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d +++ b/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d @@ -10,6 +10,6 @@ Disassembly of section .text: [0-9a-f]+ <_start>: .*:[ ]+[0-9a-f]+[ ]+auipc[ ]+a1.* -.*:[ ]+[0-9a-f]+[ ]+addi?[ ]+a0,gp.*<data_a> -.*:[ ]+[0-9a-f]+[ ]+addi?[ ]+a1,a1.*<data_b> +.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a0,gp.*<data_a> +.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a1,a1.*<data_b> #pass diff --git a/ld/testsuite/ld-riscv-elf/relax-max-align-gp.d b/ld/testsuite/ld-riscv-elf/relax-max-align-gp.d index 637de42..b62d388 100644 --- a/ld/testsuite/ld-riscv-elf/relax-max-align-gp.d +++ b/ld/testsuite/ld-riscv-elf/relax-max-align-gp.d @@ -8,7 +8,7 @@ Disassembly of section .text: 0+[0-9a-f]+ <_start>: -.*:[ ]+[0-9a-f]+[ ]+add[ ]+.*<gdata> +.*:[ ]+[0-9a-f]+[ ]+addi[ ]+.*<gdata> .*:[ ]+[0-9a-f]+[ ]+jal[ ]+.* .*:[ ]+[0-9a-f]+[ ]+j[ ]+.* .*:[ ]+[0-9a-f]+[ ]+nop diff --git a/ld/testsuite/ld-riscv-elf/weakref32.d b/ld/testsuite/ld-riscv-elf/weakref32.d index 8458f48..279481d 100644 --- a/ld/testsuite/ld-riscv-elf/weakref32.d +++ b/ld/testsuite/ld-riscv-elf/weakref32.d @@ -9,12 +9,12 @@ Disassembly of section \.text: 90000004: 02078663 beqz a5,90000030 <_start\+0x30> 90000008: 00000793 li a5,0 9000000c: 02078263 beqz a5,90000030 <_start\+0x30> -90000010: ff010113 addi? sp,sp,-16 +90000010: ff010113 addi sp,sp,-16 90000014: 00112623 sw ra,12\(sp\) 90000018: 00000097 auipc ra,0x0 9000001c: 000000e7 jalr zero # 0 <_start\-0x90000000> 90000020: 00c12083 lw ra,12\(sp\) -90000024: 01010113 addi? sp,sp,16 +90000024: 01010113 addi sp,sp,16 90000028: 00000317 auipc t1,0x0 9000002c: 00000067 jr zero # 0 <_start\-0x90000000> 90000030: 00008067 ret diff --git a/ld/testsuite/ld-riscv-elf/weakref64.d b/ld/testsuite/ld-riscv-elf/weakref64.d index 8df924e..c8f4c10 100644 --- a/ld/testsuite/ld-riscv-elf/weakref64.d +++ b/ld/testsuite/ld-riscv-elf/weakref64.d @@ -9,12 +9,12 @@ Disassembly of section \.text: 90000004: 02078663 beqz a5,90000030 <_start\+0x30> 90000008: 00000793 li a5,0 9000000c: 02078263 beqz a5,90000030 <_start\+0x30> - 90000010: ff010113 addi? sp,sp,-16 + 90000010: ff010113 addi sp,sp,-16 90000014: 00113423 sd ra,8\(sp\) 90000018: 00000097 auipc ra,0x0 9000001c: 000000e7 jalr zero # 0 <_start\-0x90000000> 90000020: 00813083 ld ra,8\(sp\) - 90000024: 01010113 addi? sp,sp,16 + 90000024: 01010113 addi sp,sp,16 90000028: 00000317 auipc t1,0x0 9000002c: 00000067 jr zero # 0 <_start\-0x90000000> 90000030: 00008067 ret |