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author | Claudiu Zissulescu <claziss@synopsys.com> | 2023-09-25 10:55:51 +0300 |
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committer | Claudiu Zissulescu <claziss@gmail.com> | 2023-09-25 10:55:51 +0300 |
commit | 6e467e9a94c1135bd11d985e9263d43204a9258b (patch) | |
tree | ec2fcd82d745b760ff71a568d8998cc8d44ba8ce /ld | |
parent | 462693a455f04fc52c1c91ffc52ea2446a086444 (diff) | |
download | gdb-6e467e9a94c1135bd11d985e9263d43204a9258b.zip gdb-6e467e9a94c1135bd11d985e9263d43204a9258b.tar.gz gdb-6e467e9a94c1135bd11d985e9263d43204a9258b.tar.bz2 |
arc: Add new LD tests for ARCv3.
Add new linker tests for ARCv3 ISA. All the new tests are added in a
distinct new folder named arc64.
ld/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd: New file.
* ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd: Likewise.
* ld/testsuite/ld-arc64/arcv3_64-reloc-near.s: Likewise.
* ld/testsuite/ld-arc64/arcv3_64.exp: Likewise.
* ld/testsuite/ld-arc64/bl34.dd: Likewise.
* ld/testsuite/ld-arc64/bl34.s: Likewise.
* ld/testsuite/ld-arc64/linkscript.ld: Likewise.
* ld/testsuite/ld-arc64/plt34-got.dd: Likewise.
* ld/testsuite/ld-arc64/plt34-got.s: Likewise.
* ld/testsuite/ld-arc64/plt34-reloc.dd: Likewise.
* ld/testsuite/ld-arc64/plt34-reloc.s: Likewise.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
Diffstat (limited to 'ld')
-rw-r--r-- | ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd | 29 | ||||
-rw-r--r-- | ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd | 21 | ||||
-rw-r--r-- | ld/testsuite/ld-arc64/arcv3_64-reloc-near.s | 11 | ||||
-rw-r--r-- | ld/testsuite/ld-arc64/arcv3_64.exp | 48 | ||||
-rw-r--r-- | ld/testsuite/ld-arc64/bl34.dd | 12 | ||||
-rw-r--r-- | ld/testsuite/ld-arc64/bl34.s | 13 | ||||
-rw-r--r-- | ld/testsuite/ld-arc64/linkscript.ld | 5 | ||||
-rw-r--r-- | ld/testsuite/ld-arc64/plt34-got.dd | 9 | ||||
-rw-r--r-- | ld/testsuite/ld-arc64/plt34-got.s | 9 | ||||
-rw-r--r-- | ld/testsuite/ld-arc64/plt34-reloc.dd | 12 | ||||
-rw-r--r-- | ld/testsuite/ld-arc64/plt34-reloc.s | 14 |
11 files changed, 183 insertions, 0 deletions
diff --git a/ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd b/ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd new file mode 100644 index 0000000..2c77c41 --- /dev/null +++ b/ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd @@ -0,0 +1,29 @@ +# an exemplary output +# +# test_static.exe: file format elf64-littlearc64 +# +# +# Disassembly of section .text: +# +# 0000000000001000 <__start>: +# 1000: 78e0 nop_s +# 1002: 2731 ff0e 0000 7000 ldl r14,[pcl,28672@s32] ;8000 <.got> +# 1006: R_ARC_GOTPC32 foo +# 100a: 2731 ff0f 0000 7000 ldl r15,[pcl,28672@s32] ;8008 <.got+0x8> +# 100e: R_ARC_GOTPC32 bar +# 1012: 78e0 nop_s +# 1014: 0000 0000 b 0 ;1014 <__start+0x14> + +[^:]+:\s+file format elf.*-.*arc64 + + +Disassembly of section .text: + +^[0-9a-f]+.*: +\s*[0-9a-f]+:\s+[0-9a-f\s]+nop_s +\s*[0-9a-f]+:\s+[0-9a-f\s]+ldl\s+r14,.* +\s*[0-9a-f]+:\s+R_ARC_GOTPC32\s+foo +\s*[0-9a-f]+:\s+[0-9a-f\s]+ldl\s+r15,.* +\s*[0-9a-f]+:\s+R_ARC_GOTPC32\s+bar +\s*[0-9a-f]+:\s+[0-9a-f\s]+nop_s +\s*[0-9a-f]+:.* diff --git a/ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd b/ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd new file mode 100644 index 0000000..2b3cef9 --- /dev/null +++ b/ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd @@ -0,0 +1,21 @@ +# an exemplary output +# +# test_dynamic.so: file format elf64-littlearc64 +# +# +# Disassembly of section .got: +# +# 0000000000002440 <.got>: +# ... +# 2440: R_ARC_GLOB_DAT foo +# 2448: R_ARC_GLOB_DAT bar + +[^:]+:\s+file format elf.*-.*arc64 + + +Disassembly of section .got: + +^[0-9a-f]+.*: +\s*\.\.\. +\s*[0-9a-f]+:\s+R_ARC_GLOB_DAT\s+foo +\s*[0-9a-f]+:\s+R_ARC_GLOB_DAT\s+bar diff --git a/ld/testsuite/ld-arc64/arcv3_64-reloc-near.s b/ld/testsuite/ld-arc64/arcv3_64-reloc-near.s new file mode 100644 index 0000000..1423f92 --- /dev/null +++ b/ld/testsuite/ld-arc64/arcv3_64-reloc-near.s @@ -0,0 +1,11 @@ + .comm foo,4 + .comm bar,4 + + .text + .align 8 + + .global __start +__start: + nop_s # messing with the alignment a bit + ldl r14, [pcl, @foo@gotpc] + ldl r15, [pcl, @bar@gotpc] diff --git a/ld/testsuite/ld-arc64/arcv3_64.exp b/ld/testsuite/ld-arc64/arcv3_64.exp new file mode 100644 index 0000000..0888db9 --- /dev/null +++ b/ld/testsuite/ld-arc64/arcv3_64.exp @@ -0,0 +1,48 @@ +# Copyright (C) 2023 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. +# + +if { ![istarget arc64-*-*] } { + return +} + +set arcv3_64_tests { + { "Near relocations (executable)" + "-q" "" "" {arcv3_64-reloc-near.s} + { { objdump { -Dr -j .text } arcv3_64-reloc-near-exe.dd } } + "arcv3_64-reloc.exe" } + { "Near relocations (shared object)" + "-shared -q -m arc64linux64" "" "" {arcv3_64-reloc-near.s} + { { objdump -DRj.got arcv3_64-reloc-near-so.dd } } + "arcv3_64-reloc-near.so" } + { "Solve fixed PLT34 reloc" + "-q -T linkscript.ld" "" "" {plt34-reloc.s} + { { objdump -drj.text plt34-reloc.dd } } + "plt34-reloc.x" } + { "Generate PLT entry using PLT34 reloc" + "-shared -m arc64linux64" "" "" {plt34-got.s} + { { objdump -dj.text plt34-got.dd } } + "plt34-got.so" } + { "Solve PCLO32_ME_2 reloc" + "-q -T linkscript.ld" "" "" {bl34.s} + { { objdump -drj.text bl34.dd } } + "bl34.x" } +} + +run_ld_link_tests $arcv3_64_tests diff --git a/ld/testsuite/ld-arc64/bl34.dd b/ld/testsuite/ld-arc64/bl34.dd new file mode 100644 index 0000000..4f983ec --- /dev/null +++ b/ld/testsuite/ld-arc64/bl34.dd @@ -0,0 +1,12 @@ +[^:]+:\s+file format elf64-.*arc64 + + +Disassembly of section .text: + +^[0-9a-f]+ <__start>: +^\s*[0-9a-f]+:\s+78e0\s+nop_s$ +^\s*[0-9a-f]+:\s+7be0\s4000\s0000\s+bl_s\s\d+@s32\s;100000000\s<foo>$ +^\s*[0-9a-f]+:\s+R_ARC_PCLO32_ME_2\s+\.text2$ +^\s*[0-9a-f]+:\s+7be0\s3fff\sfffe\s+bl_s\s\d+@s32\s;100000000\s<foo>$ +^\s*[0-9a-f]+:\s+R_ARC_PCLO32_ME_2\s+\.text2$ +^\s*[0-9a-f]+:\s+78e0\s+nop_s$ diff --git a/ld/testsuite/ld-arc64/bl34.s b/ld/testsuite/ld-arc64/bl34.s new file mode 100644 index 0000000..dfda091 --- /dev/null +++ b/ld/testsuite/ld-arc64/bl34.s @@ -0,0 +1,13 @@ + .text + .align 4 + .global __start +__start: + nop_s + bl_s @foo@s32 + bl_s @foo@s32 + +;;; Have a symbol beyond 4G boundary. + .section ".foo.text" + .align 4 +foo: + add r0,r0,r0 diff --git a/ld/testsuite/ld-arc64/linkscript.ld b/ld/testsuite/ld-arc64/linkscript.ld new file mode 100644 index 0000000..bddc653 --- /dev/null +++ b/ld/testsuite/ld-arc64/linkscript.ld @@ -0,0 +1,5 @@ +SECTIONS +{ + .text 0x00 : { *(.text) } + .text2 0x100000000 : { *(.foo.text) } +} diff --git a/ld/testsuite/ld-arc64/plt34-got.dd b/ld/testsuite/ld-arc64/plt34-got.dd new file mode 100644 index 0000000..3f57f6a --- /dev/null +++ b/ld/testsuite/ld-arc64/plt34-got.dd @@ -0,0 +1,9 @@ +[^:]+:\s+file format elf64-.*arc64 + + +Disassembly of section .text: + +^[0-9a-f]+ <__start>: +^\s*[0-9a-f]+:\s+78e0\s+nop_s$ +^\s*[0-9a-f]+:\s+[0-9a-f]+\s[0-9a-f]+\s+bl\s+[\-0-9]+\s+;[0-9a-f]+\s+<\.plt\+0x[0-9a-f]+>$ +^\s*[0-9a-f]+:\s+7be0\s[0-9a-f]+\s[0-9a-f]+\s+bl_s\s+[\-\d]+@s32\s+;[0-9a-f]+\s+<\.plt\+0x[0-9a-f]+>$
\ No newline at end of file diff --git a/ld/testsuite/ld-arc64/plt34-got.s b/ld/testsuite/ld-arc64/plt34-got.s new file mode 100644 index 0000000..a74c321 --- /dev/null +++ b/ld/testsuite/ld-arc64/plt34-got.s @@ -0,0 +1,9 @@ +;;; Check if 34bit reloc is correctly solved by the linker. + .text + .align 4 + .global __start +__start: + nop_s + bl @foo@plt + bl_s @foo@plt34 + diff --git a/ld/testsuite/ld-arc64/plt34-reloc.dd b/ld/testsuite/ld-arc64/plt34-reloc.dd new file mode 100644 index 0000000..36427a5 --- /dev/null +++ b/ld/testsuite/ld-arc64/plt34-reloc.dd @@ -0,0 +1,12 @@ +[^:]+:\s+file format elf64-.*arc64 + + +Disassembly of section .text: + +^[0-9a-f]+ <__start>: +^\s*[0-9a-f]+:\s+78e0\s+nop_s$ +^\s*[0-9a-f]+:\s+7be0\s4000\s0000\s+bl_s\s\d+@s32\s;100000000\s<foo>$ +^\s*[0-9a-f]+:\s+R_ARC_PLT34\s+foo$ +^\s*[0-9a-f]+:\s+7be0\s3fff\sfffe\s+bl_s\s\d+@s32\s;100000000\s<foo>$ +^\s*[0-9a-f]+:\s+R_ARC_PLT34\s+foo$ +^\s*[0-9a-f]+:\s+78e0\s+nop_s$ diff --git a/ld/testsuite/ld-arc64/plt34-reloc.s b/ld/testsuite/ld-arc64/plt34-reloc.s new file mode 100644 index 0000000..2be4aaf --- /dev/null +++ b/ld/testsuite/ld-arc64/plt34-reloc.s @@ -0,0 +1,14 @@ +;;; Check if 34bit reloc is correctly solved by the linker. + .text + .align 4 + .global __start +__start: + nop_s + bl_s @foo@plt34 + bl_s @foo@plt34 + +;;; Have a symbol beyond 4G boundary. + .section ".foo.text" + .align 4 +foo: + add r0,r0,r0 |