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| author | Jiong Wang <jiong.wang@arm.com> | 2015-06-01 10:31:38 +0100 |
|---|---|---|
| committer | Jiong Wang <jiong.wang@arm.com> | 2015-06-01 10:31:38 +0100 |
| commit | 36e6c1400b94b9da7ba0dff5b3900a8d3e3b0c75 (patch) | |
| tree | 3d1ec0ddf403d51adf334e946862bf15befff7c7 /ld | |
| parent | 99ad26cb0d4f9152dbe5ed03b74020cc52d84d94 (diff) | |
| download | gdb-36e6c1400b94b9da7ba0dff5b3900a8d3e3b0c75.zip gdb-36e6c1400b94b9da7ba0dff5b3900a8d3e3b0c75.tar.gz gdb-36e6c1400b94b9da7ba0dff5b3900a8d3e3b0c75.tar.bz2 | |
[AArch64] BFD_RELOC_AARCH64_TLSLE_ADD_LO12 should enable overflow check
BFD_RELOC_AARCH64_TLSLE_ADD_LO12 is used to generate simplest
one-instruction addressing for TLS LE model when tls size is smaller
4K. Linker need to make sure there is no TLS offset overflow.
2015-06-01 Jiong Wang <jiong.wang@arm.com>
bfd/
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Set overflow type to
complain_overflow_unsigned for BFD_RELOC_AARCH64_TLSLE_ADD_LO12.
* elfxx-aarch64.c (_bfd_aarch64_elf_resolve_relocation): Don't use
PGOFF for BFD_RELOC_AARCH64_TLSLE_ADD_LO12, that will mask off all
potential high overflowed bits.
ld/testsuite/
* ld-aarch64/tprel_add_lo12_overflow.s: New testcase.
* ld-aarch64/tprel_add_lo12_overflow.d: Nex expectation file.
* ld-aarch64/aarch64-elf.exp: Run new testcase.
Diffstat (limited to 'ld')
| -rw-r--r-- | ld/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | ld/testsuite/ld-aarch64/aarch64-elf.exp | 1 | ||||
| -rw-r--r-- | ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.d | 6 | ||||
| -rw-r--r-- | ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.s | 23 |
4 files changed, 36 insertions, 0 deletions
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index 9857040..b03786c 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2015-06-01 Jiong Wang <jiong.wang@arm.com> + * ld-aarch64/tprel_add_lo12_overflow.s: New testcase. + * ld-aarch64/tprel_add_lo12_overflow.d: Nex expectation file. + * ld-aarch64/aarch64-elf.exp: Run new testcase. + +2015-06-01 Jiong Wang <jiong.wang@arm.com> + * ld-aarch64/emit-relocs-313.s: New test file. * ld-aarch64/emit-relocs-313.d: Ditto. * ld-aarch64/aarch64-elf.exp: Run new test. diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp index 79b5a3e..09f2a0e 100644 --- a/ld/testsuite/ld-aarch64/aarch64-elf.exp +++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp @@ -146,6 +146,7 @@ run_dump_test "gc-relocs-257-dyn" run_dump_test "gc-relocs-257" run_dump_test "pr17415" run_dump_test "tprel_g2_overflow" +run_dump_test "tprel_add_lo12_overflow" # ifunc tests run_dump_test "ifunc-1" diff --git a/ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.d b/ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.d new file mode 100644 index 0000000..297ee22 --- /dev/null +++ b/ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.d @@ -0,0 +1,6 @@ +#name: TLS offset out of range - TPREL_ADD_LO12 +#source: tprel_add_lo12_overflow.s +#as: +#ld: -e0 +#error: .*\(.text\+0x\d+\): relocation truncated to fit: R_AARCH64_TLSLE_ADD_TPREL_LO12 against symbol `i' .* + diff --git a/ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.s b/ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.s new file mode 100644 index 0000000..7c93d0d --- /dev/null +++ b/ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.s @@ -0,0 +1,23 @@ + .cpu generic + .global ff + .section .tdata,"awT",%progbits + .align 2 + .type ff, %object + # Maximum 12bit - 16byte TCB header is the upper limit + # for tprel_add_lo12 + .size ff, 4096 - 16 +ff: + .zero 4096 - 16 + .global i + .type i, %object + .size i, 4 +i: + .zero 4 + .text + .align 2 + .global main + .type main, %function +main: + add x0, x0, #:tprel_lo12:i + ret + .size main, .-main |