diff options
| author | Alan Modra <amodra@gmail.com> | 2007-02-12 12:02:58 +0000 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2007-02-12 12:02:58 +0000 |
| commit | 84f5d08e6b2cc79becc9a7dcad5c4ad9ba1959b1 (patch) | |
| tree | c0ea8ebea1953e5b0c523748d4a1aae3f9c84b28 /ld | |
| parent | 4aac632ee9db7d3ff11e6ee1ca4f487ac6868e46 (diff) | |
| download | gdb-84f5d08e6b2cc79becc9a7dcad5c4ad9ba1959b1.zip gdb-84f5d08e6b2cc79becc9a7dcad5c4ad9ba1959b1.tar.gz gdb-84f5d08e6b2cc79becc9a7dcad5c4ad9ba1959b1.tar.bz2 | |
bfd/
* elf64-ppc.c (create_linkage_sections): Don't create
.rela.rodata.brlt for --emit-relocs.
(ppc_build_one_stub): Create relocs for brlt --emit-relocs here.
(ppc_size_one_stub): Count them. Simplify test of stub type
when counting stub relocs. Set SEC_RELOC too.
(ppc64_elf_size_stubs): Clear reloc_count and SEC_RELOC.
(ppc64_elf_finish_dynamic_sections): Output brlt relocs.
ld/testsuite/
* ld-powerpc/relbrlt.d: Update.
Diffstat (limited to 'ld')
| -rw-r--r-- | ld/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | ld/testsuite/ld-powerpc/relbrlt.d | 66 |
2 files changed, 37 insertions, 33 deletions
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index 455be58..fbd449a 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2007-02-12 Alan Modra <amodra@bigpond.net.au> + + * ld-powerpc/relbrlt.d: Update. + 2007-02-06 Nick Clifton <nickc@redhat.com> PR ld/3805 diff --git a/ld/testsuite/ld-powerpc/relbrlt.d b/ld/testsuite/ld-powerpc/relbrlt.d index 3638072..7622ed6 100644 --- a/ld/testsuite/ld-powerpc/relbrlt.d +++ b/ld/testsuite/ld-powerpc/relbrlt.d @@ -7,44 +7,44 @@ Disassembly of section \.text: -0*100000a8 <_start>: - 100000a8: 49 bf 00 31 bl 11bf00d8 .* - 100000a8: R_PPC64_REL24 \.text\+0x37e0044 - 100000ac: 60 00 00 00 nop - 100000b0: 49 bf 00 19 bl 11bf00c8 .* - 100000b0: R_PPC64_REL24 \.text\+0x3bf0020 - 100000b4: 60 00 00 00 nop - 100000b8: 49 bf 00 25 bl 11bf00dc .* - 100000b8: R_PPC64_REL24 \.text\+0x57e0024 - 100000bc: 60 00 00 00 nop - 100000c0: 00 00 00 00 \.long 0x0 - 100000c4: 4b ff ff e4 b 100000a8 <_start> +0*10000078 <_start>: + 10000078: 49 bf 00 31 bl 11bf00a8 .* + 10000078: R_PPC64_REL24 \.text\+0x37e0044 + 1000007c: 60 00 00 00 nop + 10000080: 49 bf 00 19 bl 11bf0098 .* + 10000080: R_PPC64_REL24 \.text\+0x3bf0020 + 10000084: 60 00 00 00 nop + 10000088: 49 bf 00 25 bl 11bf00ac .* + 10000088: R_PPC64_REL24 \.text\+0x57e0024 + 1000008c: 60 00 00 00 nop + 10000090: 00 00 00 00 \.long 0x0 + 10000094: 4b ff ff e4 b 10000078 <_start> \.\.\. -0*11bf00c8 <.*plt_branch.*>: - 11bf00c8: 3d 82 05 7e addis r12,r2,1406 - 11bf00cc: e9 6c 80 58 ld r11,-32680\(r12\) - 11bf00d0: 7d 69 03 a6 mtctr r11 - 11bf00d4: 4e 80 04 20 bctr - -0*11bf00d8 <.*long_branch.*>: - 11bf00d8: 49 bf 00 14 b 137e00ec <far> - 11bf00d8: R_PPC64_REL24 \*ABS\*\+0x137e00ec - -0*11bf00dc <.*plt_branch.*>: - 11bf00dc: 3d 82 05 7e addis r12,r2,1406 - 11bf00e0: e9 6c 80 60 ld r11,-32672\(r12\) - 11bf00e4: 7d 69 03 a6 mtctr r11 - 11bf00e8: 4e 80 04 20 bctr +0*11bf0098 <.*plt_branch.*>: + 11bf0098: 3d 82 05 7e addis r12,r2,1406 + 11bf009c: e9 6c 80 28 ld r11,-32728\(r12\) + 11bf00a0: 7d 69 03 a6 mtctr r11 + 11bf00a4: 4e 80 04 20 bctr + +0*11bf00a8 <.*long_branch.*>: + 11bf00a8: 49 bf 00 14 b 137e00bc <far> + 11bf00a8: R_PPC64_REL24 \*ABS\*\+0x137e00bc + +0*11bf00ac <.*plt_branch.*>: + 11bf00ac: 3d 82 05 7e addis r12,r2,1406 + 11bf00b0: e9 6c 80 30 ld r11,-32720\(r12\) + 11bf00b4: 7d 69 03 a6 mtctr r11 + 11bf00b8: 4e 80 04 20 bctr \.\.\. -0*137e00ec <far>: - 137e00ec: 4e 80 00 20 blr +0*137e00bc <far>: + 137e00bc: 4e 80 00 20 blr \.\.\. -0*13bf00c8 <far2far>: - 13bf00c8: 4e 80 00 20 blr +0*13bf0098 <far2far>: + 13bf0098: 4e 80 00 20 blr \.\.\. -0*157e00cc <huge>: - 157e00cc: 4e 80 00 20 blr +0*157e009c <huge>: + 157e009c: 4e 80 00 20 blr |