ld/

    * emultempl/armelf.em (fix_cortex_a8): New.
    (arm_elf_before_allocation): Call bfd_elf32_arm_set_cortex_a8_fix.
    (arm_elf_create_output_section_statements): Add fix_cortex_a8 to
    bfd_elf32_arm_set_target_relocs.
    (OPTION_FIX_CORTEX_A8, OPTION_NO_FIX_CORTEX_A8): New.
    (PARSE_AND_LIST_LONGOPTS): Add [no-]fix-cortex-a8 options.
    (PARSE_AND_LIST_OPTIONS): Add [no-]fix-cortex-a8 options.
    (PARSE_AND_LIST_ARGS_CASES): Handle OPTION_[NO_]FIX_CORTEX_A8.
    * ld.texinfo (--[no-]fix-cortex-a8): Briefly document new options.

    bfd/
    * elf32-arm.c (THUMB16_BCOND_INSN, THUMB32_INSN, THUMB32_B_INSN):
    New macros.
    (elf32_arm_stub_a8_veneer_b_cond, elf32_arm_stub_a8_veneer_b)
    (elf32_arm_stub_a8_veneer_blx): New stub sequences.
    (elf32_arm_stub_type): Add arm_stub_a8_veneer_b_cond,
    arm_stub_a8_veneer_b and arm_stub_a8_veneer_blx.
    (elf32_arm_stub_hash_entry): Add target_addend, orig_insn fields.
    (a8_erratum_fix, a8_erratum_reloc): New structs.
    (elf32_arm_link_hash_table): Add a8_erratum_fixes,
    num_a8_erratum_fixes, fix_cortex_a8 fields.
    (elf32_arm_link_hash_table_create): Zero fix_cortex_a8.
    (elf32_arm_add_stub): Split into two parts, creating...
    (elf32_arm_create_or_find_stub_sec): New function.
    (elf32_arm_final_link_relocate): Add forward declaration.
    (arm_build_one_stub): Add support for THUMB32_TYPE, Thumb-2
    relocations, multiple relocations per stub.
    (find_stub_size_and_template): New (using parts of
    arm_size_one_stub).
    (arm_size_one_stub): Use find_stub_size_and_template.
    (a8_reloc_compare): New.
    (find_thumb_glue): Add forward declaration.
    (cortex_a8_erratum_scan): New.
    (elf32_arm_size_stubs): Add Cortex-A8 erratum workaround support.
    (bfd_elf32_arm_set_cortex_a8_fix): New.
    (bfd_elf32_arm_set_target_relocs): Add fix_cortex_a8 argument.
    (arm_map_one_stub): Add THUMB32_TYPE support.
    (a8_branch_to_stub_data): New.
    (make_branch_to_a8_stub): New.
    (elf32_arm_write_section): Add Cortex-A8 erratum workaround support.
    * bfd-in.h (bfd_elf32_arm_set_cortex_a8_fix): New.
    (bfd_elf32_arm_set_target_relocs): Add argument for controlling
    Cortex-A8 erratum workaround.
    * bfd-in2.h: Regenerate.

    ld/testsuite/
    * ld-arm/cortex-a8-arm-target.s: New.
    * ld-arm/cortex-a8-thumb-target.s: New.
    * ld-arm/cortex-a8-fix-b-rel.s: New.
    * ld-arm/cortex-a8-fix-b-rel-arm.d: New.
    * ld-arm/cortex-a8-fix-b-rel-thumb.d: New.
    * ld-arm/cortex-a8-fix-b.s: New.
    * ld-arm/cortex-a8-fix-b.d: New.
    * ld-arm/cortex-a8-fix-bl-rel.s: New.
    * ld-arm/cortex-a8-fix-bl-rel-arm.d: New.
    * ld-arm/cortex-a8-fix-bl-rel-thumb.d: New.
    * ld-arm/cortex-a8-fix-bl.s: New.
    * ld-arm/cortex-a8-fix-bl.d: New.
    * ld-arm/cortex-a8-fix-bcc-rel.s: New.
    * ld-arm/cortex-a8-fix-bcc-rel-thumb.d: New.
    * ld-arm/cortex-a8-fix-bcc.s: New.
    * ld-arm/cortex-a8-fix-bcc.d: New.
    * ld-arm/cortex-a8-fix-blx-rel.s: New.
    * ld-arm/cortex-a8-fix-blx-rel-arm.d: New.
    * ld-arm/cortex-a8-fix-blx-rel-thumb.d: New.
    * ld-arm/cortex-a8-fix-blx.s: New.
    * ld-arm/cortex-a8-fix-blx.d: New.
    * ld-arm/arm-elf.exp: Add new tests.

23 files changed, 1275 insertions, 0 deletions

diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index 0df5dbc..1613b29 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,28 @@
+2009-05-22  Julian Brown  <julian@codesourcery.com>
+
+	* ld-arm/cortex-a8-arm-target.s: New.
+	* ld-arm/cortex-a8-thumb-target.s: New.
+	* ld-arm/cortex-a8-fix-b-rel.s: New.
+	* ld-arm/cortex-a8-fix-b-rel-arm.d: New.
+	* ld-arm/cortex-a8-fix-b-rel-thumb.d: New.
+	* ld-arm/cortex-a8-fix-b.s: New.
+	* ld-arm/cortex-a8-fix-b.d: New.
+	* ld-arm/cortex-a8-fix-bl-rel.s: New.
+	* ld-arm/cortex-a8-fix-bl-rel-arm.d: New.
+	* ld-arm/cortex-a8-fix-bl-rel-thumb.d: New.
+	* ld-arm/cortex-a8-fix-bl.s: New.
+	* ld-arm/cortex-a8-fix-bl.d: New.
+	* ld-arm/cortex-a8-fix-bcc-rel.s: New.
+	* ld-arm/cortex-a8-fix-bcc-rel-thumb.d: New.
+	* ld-arm/cortex-a8-fix-bcc.s: New.
+	* ld-arm/cortex-a8-fix-bcc.d: New.
+	* ld-arm/cortex-a8-fix-blx-rel.s: New.
+	* ld-arm/cortex-a8-fix-blx-rel-arm.d: New.
+	* ld-arm/cortex-a8-fix-blx-rel-thumb.d: New.
+	* ld-arm/cortex-a8-fix-blx.s: New.
+	* ld-arm/cortex-a8-fix-blx.d: New.
+	* ld-arm/arm-elf.exp: Add new tests.
+
 2009-05-22  Nathan Sidwell  <nathan@codesourcery.com>
 
 	* ld-scripts/rgn-at4.t: New.
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index 4e8a933..de3628e 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -161,6 +161,50 @@ set armelftests {
      "-EL --vfp11-denorm-fix=scalar -Ttext=0x8000" "-EL -mfpu=vfpxd" {vfp11-fix-none.s}
      {{objdump -dr vfp11-fix-none.d}}
      "vfp11-fix-none"}
+    {"Cortex-A8 erratum fix, b.w"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-b.s}
+     {{objdump -dr cortex-a8-fix-b.d}}
+     "cortex-a8-fix-b"}
+    {"Cortex-A8 erratum fix, bl.w"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-bl.s}
+     {{objdump -dr cortex-a8-fix-bl.d}}
+     "cortex-a8-fix-bl"}
+    {"Cortex-A8 erratum fix, bcc.w"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-bcc.s}
+     {{objdump -dr cortex-a8-fix-bcc.d}}
+     "cortex-a8-fix-bcc"}
+    {"Cortex-A8 erratum fix, blx.w"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-blx.s}
+     {{objdump -dr cortex-a8-fix-blx.d}}
+     "cortex-a8-fix-blx"}
+    {"Cortex-A8 erratum fix, relocate b.w to ARM"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-arm-target.s cortex-a8-fix-b-rel.s}
+     {{objdump -dr cortex-a8-fix-b-rel-arm.d}}
+     "cortex-a8-fix-b-rel-arm"}
+    {"Cortex-A8 erratum fix, relocate b.w to Thumb"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-b-rel.s}
+     {{objdump -dr cortex-a8-fix-b-rel-thumb.d}}
+     "cortex-a8-fix-b-rel-thumb"}
+    {"Cortex-A8 erratum fix, relocate bl.w to ARM"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-arm-target.s cortex-a8-fix-bl-rel.s}
+     {{objdump -dr cortex-a8-fix-bl-rel-arm.d}}
+     "cortex-a8-fix-bl-rel-arm"}
+    {"Cortex-A8 erratum fix, relocate bl.w to Thumb"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-bl-rel.s}
+     {{objdump -dr cortex-a8-fix-bl-rel-thumb.d}}
+     "cortex-a8-fix-bl-rel-thumb"}
+    {"Cortex-A8 erratum fix, relocate b<cond>.w to Thumb"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-bcc-rel.s}
+     {{objdump -dr cortex-a8-fix-bcc-rel-thumb.d}}
+     "cortex-a8-fix-bcc-rel-thumb"}
+    {"Cortex-A8 erratum fix, relocate blx.w to ARM"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-arm-target.s cortex-a8-fix-blx-rel.s}
+     {{objdump -dr cortex-a8-fix-blx-rel-arm.d}}
+     "cortex-a8-fix-blx-rel-arm"}
+    {"Cortex-A8 erratum fix, relocate blx.w to Thumb"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-blx-rel.s}
+     {{objdump -dr cortex-a8-fix-blx-rel-thumb.d}}
+     "cortex-a8-fix-blx-rel-thumb"}
     {"Unwinding and -gc-sections" "-gc-sections" "" {gc-unwind.s}
      {{objdump -sj.data gc-unwind.d}}
      "gc-unwind"}
diff --git a/ld/testsuite/ld-arm/cortex-a8-arm-target.s b/ld/testsuite/ld-arm/cortex-a8-arm-target.s
new file mode 100644
index 0000000..d5174c4
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-arm-target.s
@@ -0,0 +1,9 @@
+	.syntax unified
+	.cpu cortex-a8
+	.text
+	.arm
+	.align 3
+	.global targetfn
+	.type targetfn, %function
+targetfn:
+	bx lr
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d b/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d
new file mode 100644
index 0000000..0a2b0bd
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d
@@ -0,0 +1,83 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <targetfn>:
+    8f00:	e12fff1e 	bx	lr
+    8f04:	e320f000 	nop	\{0\}
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f000 b87f 	b\.w	9010 <__targetfn_from_thumb>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f000 b87b 	b\.w	9010 <__targetfn_from_thumb>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f000 b877 	b\.w	9010 <__targetfn_from_thumb>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f000 b873 	b\.w	9010 <__targetfn_from_thumb>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f000 b86f 	b\.w	9010 <__targetfn_from_thumb>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f000 b86b 	b\.w	9010 <__targetfn_from_thumb>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f000 b867 	b\.w	9010 <__targetfn_from_thumb>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f000 b863 	b\.w	9010 <__targetfn_from_thumb>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f000 b85f 	b\.w	9010 <__targetfn_from_thumb>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f000 b85b 	b\.w	9010 <__targetfn_from_thumb>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f000 b857 	b\.w	9010 <__targetfn_from_thumb>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f000 b853 	b\.w	9010 <__targetfn_from_thumb>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f000 b84f 	b\.w	9010 <__targetfn_from_thumb>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f000 b84b 	b\.w	9010 <__targetfn_from_thumb>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f000 b847 	b\.w	9010 <__targetfn_from_thumb>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f000 b843 	b\.w	9010 <__targetfn_from_thumb>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f000 b83f 	b\.w	9010 <__targetfn_from_thumb>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f000 b83b 	b\.w	9010 <__targetfn_from_thumb>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f000 b837 	b\.w	9010 <__targetfn_from_thumb>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f000 b833 	b\.w	9010 <__targetfn_from_thumb>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f000 b82f 	b\.w	9010 <__targetfn_from_thumb>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f000 b82b 	b\.w	9010 <__targetfn_from_thumb>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f000 b827 	b\.w	9010 <__targetfn_from_thumb>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f000 b823 	b\.w	9010 <__targetfn_from_thumb>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f000 b81f 	b\.w	9010 <__targetfn_from_thumb>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f000 b81b 	b\.w	9010 <__targetfn_from_thumb>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f000 b817 	b\.w	9010 <__targetfn_from_thumb>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f000 b813 	b\.w	9010 <__targetfn_from_thumb>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f000 b80f 	b\.w	9010 <__targetfn_from_thumb>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f000 b80b 	b\.w	9010 <__targetfn_from_thumb>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 b807 	b\.w	9010 <__targetfn_from_thumb>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f000 b803 	b\.w	9010 <__targetfn_from_thumb>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+
+00009010 <__targetfn_from_thumb>:
+    9010:	4778      	bx	pc
+    9012:	46c0      	nop			\(mov r8, r8\)
+    9014:	eaffffb9 	b	8f00 <targetfn>
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-thumb.d b/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-thumb.d
new file mode 100644
index 0000000..60a254b
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-thumb.d
@@ -0,0 +1,80 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <targetfn>:
+    8f00:	4770      	bx	lr
+    8f02:	bf00      	nop
+    8f04:	f3af 8000 	nop\.w
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff bff7 	b\.w	8f00 <targetfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff bff3 	b\.w	8f00 <targetfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff bfef 	b\.w	8f00 <targetfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff bfeb 	b\.w	8f00 <targetfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff bfe7 	b\.w	8f00 <targetfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff bfe3 	b\.w	8f00 <targetfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff bfdf 	b\.w	8f00 <targetfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff bfdb 	b\.w	8f00 <targetfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff bfd7 	b\.w	8f00 <targetfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff bfd3 	b\.w	8f00 <targetfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff bfcf 	b\.w	8f00 <targetfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff bfcb 	b\.w	8f00 <targetfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff bfc7 	b\.w	8f00 <targetfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff bfc3 	b\.w	8f00 <targetfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff bfbf 	b\.w	8f00 <targetfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff bfbb 	b\.w	8f00 <targetfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff bfb7 	b\.w	8f00 <targetfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff bfb3 	b\.w	8f00 <targetfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff bfaf 	b\.w	8f00 <targetfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff bfab 	b\.w	8f00 <targetfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff bfa7 	b\.w	8f00 <targetfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff bfa3 	b\.w	8f00 <targetfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff bf9f 	b\.w	8f00 <targetfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff bf9b 	b\.w	8f00 <targetfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff bf97 	b\.w	8f00 <targetfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff bf93 	b\.w	8f00 <targetfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff bf8f 	b\.w	8f00 <targetfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff bf8b 	b\.w	8f00 <targetfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff bf87 	b\.w	8f00 <targetfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff bf83 	b\.w	8f00 <targetfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 b807 	b\.w	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f7ff bf7b 	b\.w	8f00 <targetfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	f7ff bf76 	b\.w	8f00 <targetfn>
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-b-rel.s b/ld/testsuite/ld-arm/cortex-a8-fix-b-rel.s
new file mode 100644
index 0000000..3ec95ab
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-b-rel.s
@@ -0,0 +1,41 @@
+	.syntax unified
+	.cpu cortex-a8
+	.thumb
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+1:
+        add.w r0, r1, r2
+        b.w targetfn
+        add.w r0, r1, r2
+        b.w targetfn
+        add.w r0, r1, r2
+        b.w targetfn
+        add.w r0, r1, r2
+        b.w targetfn
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+        .align  3
+        .global _start
+        .thumb
+        .thumb_func
+        .type   _start, %function
+_start:
+	nop
+
+	@ If branching to an ARM destination, we *don't* want to create a
+	@ Cortex-A8 stub: the Thumb-to-ARM stub will suffice (and we need it
+	@ to change mode).
+	bw2
+	bw2
+
+        bx      lr
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-b.d b/ld/testsuite/ld-arm/cortex-a8-fix-b.d
new file mode 100644
index 0000000..b2d4481
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-b.d
@@ -0,0 +1,75 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <_start>:
+    8f00:	bf00      	nop
+    8f02:	eb01 0002 	add\.w	r0, r1, r2
+    8f06:	f7ff bffc 	b\.w	8f02 <_start\+0x2>
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff bff8 	b\.w	8f02 <_start\+0x2>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff bff4 	b\.w	8f02 <_start\+0x2>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff bff0 	b\.w	8f02 <_start\+0x2>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff bffc 	b\.w	8f22 <_start\+0x22>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff bff8 	b\.w	8f22 <_start\+0x22>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff bff4 	b\.w	8f22 <_start\+0x22>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff bff0 	b\.w	8f22 <_start\+0x22>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff bffc 	b\.w	8f42 <_start\+0x42>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff bff8 	b\.w	8f42 <_start\+0x42>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff bff4 	b\.w	8f42 <_start\+0x42>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff bff0 	b\.w	8f42 <_start\+0x42>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff bffc 	b\.w	8f62 <_start\+0x62>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff bff8 	b\.w	8f62 <_start\+0x62>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff bff4 	b\.w	8f62 <_start\+0x62>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff bff0 	b\.w	8f62 <_start\+0x62>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff bffc 	b\.w	8f82 <_start\+0x82>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff bff8 	b\.w	8f82 <_start\+0x82>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff bff4 	b\.w	8f82 <_start\+0x82>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff bff0 	b\.w	8f82 <_start\+0x82>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff bffc 	b\.w	8fa2 <_start\+0xa2>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff bff8 	b\.w	8fa2 <_start\+0xa2>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff bff4 	b\.w	8fa2 <_start\+0xa2>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff bff0 	b\.w	8fa2 <_start\+0xa2>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff bffc 	b\.w	8fc2 <_start\+0xc2>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff bff8 	b\.w	8fc2 <_start\+0xc2>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff bff4 	b\.w	8fc2 <_start\+0xc2>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff bff0 	b\.w	8fc2 <_start\+0xc2>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff bffc 	b\.w	8fe2 <_start\+0xe2>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff bff8 	b\.w	8fe2 <_start\+0xe2>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff bff4 	b\.w	8fe2 <_start\+0xe2>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 b803 	b\.w	9008 <_start\+0x108>
+    9002:	4770      	bx	lr
+    9004:	f3af 8000 	nop\.w
+    9008:	f7ff bfeb 	b\.w	8fe2 <_start\+0xe2>
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-b.s b/ld/testsuite/ld-arm/cortex-a8-fix-b.s
new file mode 100644
index 0000000..c0f21ac
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-b.s
@@ -0,0 +1,39 @@
+	.syntax unified
+	.cpu cortex-a8
+	.thumb
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+1:
+        add.w r0, r1, r2
+        b.w 1b
+        add.w r0, r1, r2
+        b.w 1b
+        add.w r0, r1, r2
+        b.w 1b
+        add.w r0, r1, r2
+        b.w 1b
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+        .align  3
+        .global _start
+        .thumb
+        .thumb_func
+        .type   _start, %function
+_start:
+        nop
+
+	@ Trigger Cortex-A8 erratum workaround with b instructions.
+        bw2
+        bw2
+
+        bx      lr
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel-thumb.d b/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel-thumb.d
new file mode 100644
index 0000000..27a7fd4
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel-thumb.d
@@ -0,0 +1,82 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <targetfn>:
+    8f00:	4770      	bx	lr
+    8f02:	bf00      	nop
+    8f04:	f3af 8000 	nop\.w
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f53f aff7 	bmi\.w	8f00 <targetfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f53f aff3 	bmi\.w	8f00 <targetfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f53f afef 	bmi\.w	8f00 <targetfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f53f afeb 	bmi\.w	8f00 <targetfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f53f afe7 	bmi\.w	8f00 <targetfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f53f afe3 	bmi\.w	8f00 <targetfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f53f afdf 	bmi\.w	8f00 <targetfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f53f afdb 	bmi\.w	8f00 <targetfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f53f afd7 	bmi\.w	8f00 <targetfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f53f afd3 	bmi\.w	8f00 <targetfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f53f afcf 	bmi\.w	8f00 <targetfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f53f afcb 	bmi\.w	8f00 <targetfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f53f afc7 	bmi\.w	8f00 <targetfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f53f afc3 	bmi\.w	8f00 <targetfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f53f afbf 	bmi\.w	8f00 <targetfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f53f afbb 	bmi\.w	8f00 <targetfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f53f afb7 	bmi\.w	8f00 <targetfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f53f afb3 	bmi\.w	8f00 <targetfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f53f afaf 	bmi\.w	8f00 <targetfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f53f afab 	bmi\.w	8f00 <targetfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f53f afa7 	bmi\.w	8f00 <targetfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f53f afa3 	bmi\.w	8f00 <targetfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f53f af9f 	bmi\.w	8f00 <targetfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f53f af9b 	bmi\.w	8f00 <targetfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f53f af97 	bmi\.w	8f00 <targetfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f53f af93 	bmi\.w	8f00 <targetfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f53f af8f 	bmi\.w	8f00 <targetfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f53f af8b 	bmi\.w	8f00 <targetfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f53f af87 	bmi\.w	8f00 <targetfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f53f af83 	bmi\.w	8f00 <targetfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 b807 	b\.w	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f53f af7b 	bmi\.w	8f00 <targetfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	d401      	bmi\.n	9016 <_start\+0x10e>
+    9012:	f7ff bff6 	b\.w	9002 <_start\+0xfa>
+    9016:	f7ff bf73 	b\.w	8f00 <targetfn>
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel.s b/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel.s
new file mode 100644
index 0000000..b7b9451
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel.s
@@ -0,0 +1,38 @@
+	.syntax unified
+	.cpu cortex-a8
+	.thumb
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+1:
+        add.w r0, r1, r2
+        bmi.w targetfn
+        add.w r0, r1, r2
+        bmi.w targetfn
+        add.w r0, r1, r2
+        bmi.w targetfn
+        add.w r0, r1, r2
+        bmi.w targetfn
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+        .align  3
+        .global _start
+        .thumb
+        .thumb_func
+        .type   _start, %function
+_start:
+	nop
+
+	bw2
+	bw2
+
+        bx      lr
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bcc.d b/ld/testsuite/ld-arm/cortex-a8-fix-bcc.d
new file mode 100644
index 0000000..44b8110
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-bcc.d
@@ -0,0 +1,77 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <_start>:
+    8f00:	bf00      	nop
+    8f02:	eb01 0002 	add\.w	r0, r1, r2
+    8f06:	f4ff affc 	bcc\.w	8f02 <_start\+0x2>
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f4ff aff8 	bcc\.w	8f02 <_start\+0x2>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f4ff aff4 	bcc\.w	8f02 <_start\+0x2>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f4ff aff0 	bcc\.w	8f02 <_start\+0x2>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f4ff affc 	bcc\.w	8f22 <_start\+0x22>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f4ff aff8 	bcc\.w	8f22 <_start\+0x22>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f4ff aff4 	bcc\.w	8f22 <_start\+0x22>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f4ff aff0 	bcc\.w	8f22 <_start\+0x22>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f4ff affc 	bcc\.w	8f42 <_start\+0x42>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f4ff aff8 	bcc\.w	8f42 <_start\+0x42>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f4ff aff4 	bcc\.w	8f42 <_start\+0x42>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f4ff aff0 	bcc\.w	8f42 <_start\+0x42>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f4ff affc 	bcc\.w	8f62 <_start\+0x62>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f4ff aff8 	bcc\.w	8f62 <_start\+0x62>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f4ff aff4 	bcc\.w	8f62 <_start\+0x62>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f4ff aff0 	bcc\.w	8f62 <_start\+0x62>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f4ff affc 	bcc\.w	8f82 <_start\+0x82>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f4ff aff8 	bcc\.w	8f82 <_start\+0x82>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f4ff aff4 	bcc\.w	8f82 <_start\+0x82>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f4ff aff0 	bcc\.w	8f82 <_start\+0x82>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f4ff affc 	bcc\.w	8fa2 <_start\+0xa2>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f4ff aff8 	bcc\.w	8fa2 <_start\+0xa2>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f4ff aff4 	bcc\.w	8fa2 <_start\+0xa2>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f4ff aff0 	bcc\.w	8fa2 <_start\+0xa2>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f4ff affc 	bcc\.w	8fc2 <_start\+0xc2>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f4ff aff8 	bcc\.w	8fc2 <_start\+0xc2>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f4ff aff4 	bcc\.w	8fc2 <_start\+0xc2>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f4ff aff0 	bcc\.w	8fc2 <_start\+0xc2>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f4ff affc 	bcc\.w	8fe2 <_start\+0xe2>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f4ff aff8 	bcc\.w	8fe2 <_start\+0xe2>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f4ff aff4 	bcc\.w	8fe2 <_start\+0xe2>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 b803 	b\.w	9008 <_start\+0x108>
+    9002:	4770      	bx	lr
+    9004:	f3af 8000 	nop\.w
+    9008:	d301      	bcc\.n	900e <_start\+0x10e>
+    900a:	f7ff bffa 	b\.w	9002 <_start\+0x102>
+    900e:	f7ff bfe8 	b\.w	8fe2 <_start\+0xe2>
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bcc.s b/ld/testsuite/ld-arm/cortex-a8-fix-bcc.s
new file mode 100644
index 0000000..8a667a3
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-bcc.s
@@ -0,0 +1,39 @@
+	.syntax unified
+	.cpu cortex-a8
+	.thumb
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+1:
+        add.w r0, r1, r2
+        bcc.w 1b
+        add.w r0, r1, r2
+        bcc.w 1b
+        add.w r0, r1, r2
+        bcc.w 1b
+        add.w r0, r1, r2
+        bcc.w 1b
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+        .align  3
+        .global _start
+        .thumb
+        .thumb_func
+        .type   _start, %function
+_start:
+        nop
+
+	@ Trigger Cortex-A8 erratum workaround with conditional branches.
+        bw2
+        bw2
+
+        bx      lr
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-arm.d b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-arm.d
new file mode 100644
index 0000000..fcb3bab
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-arm.d
@@ -0,0 +1,79 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <targetfn>:
+    8f00:	e12fff1e 	bx	lr
+    8f04:	e320f000 	nop	\{0\}
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff eff8 	blx	8f00 <targetfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff eff4 	blx	8f00 <targetfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff eff0 	blx	8f00 <targetfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff efec 	blx	8f00 <targetfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff efe8 	blx	8f00 <targetfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff efe4 	blx	8f00 <targetfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff efe0 	blx	8f00 <targetfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff efdc 	blx	8f00 <targetfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff efd8 	blx	8f00 <targetfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff efd4 	blx	8f00 <targetfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff efd0 	blx	8f00 <targetfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff efcc 	blx	8f00 <targetfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff efc8 	blx	8f00 <targetfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff efc4 	blx	8f00 <targetfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff efc0 	blx	8f00 <targetfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff efbc 	blx	8f00 <targetfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff efb8 	blx	8f00 <targetfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff efb4 	blx	8f00 <targetfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff efb0 	blx	8f00 <targetfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff efac 	blx	8f00 <targetfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff efa8 	blx	8f00 <targetfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff efa4 	blx	8f00 <targetfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff efa0 	blx	8f00 <targetfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff ef9c 	blx	8f00 <targetfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff ef98 	blx	8f00 <targetfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff ef94 	blx	8f00 <targetfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff ef90 	blx	8f00 <targetfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff ef8c 	blx	8f00 <targetfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff ef88 	blx	8f00 <targetfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff ef84 	blx	8f00 <targetfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 e808 	blx	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f7ff ef7c 	blx	8f00 <targetfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	eaffffba 	b	8f00 <targetfn>
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-thumb.d b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-thumb.d
new file mode 100644
index 0000000..8cbd3e0
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-thumb.d
@@ -0,0 +1,80 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <targetfn>:
+    8f00:	4770      	bx	lr
+    8f02:	bf00      	nop
+    8f04:	f3af 8000 	nop\.w
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff fff7 	bl	8f00 <targetfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff fff3 	bl	8f00 <targetfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff ffef 	bl	8f00 <targetfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff ffeb 	bl	8f00 <targetfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff ffe7 	bl	8f00 <targetfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff ffe3 	bl	8f00 <targetfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff ffdf 	bl	8f00 <targetfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff ffdb 	bl	8f00 <targetfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff ffd7 	bl	8f00 <targetfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff ffd3 	bl	8f00 <targetfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff ffcf 	bl	8f00 <targetfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff ffcb 	bl	8f00 <targetfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff ffc7 	bl	8f00 <targetfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff ffc3 	bl	8f00 <targetfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff ffbf 	bl	8f00 <targetfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff ffbb 	bl	8f00 <targetfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff ffb7 	bl	8f00 <targetfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff ffb3 	bl	8f00 <targetfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff ffaf 	bl	8f00 <targetfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff ffab 	bl	8f00 <targetfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff ffa7 	bl	8f00 <targetfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff ffa3 	bl	8f00 <targetfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff ff9f 	bl	8f00 <targetfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff ff9b 	bl	8f00 <targetfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff ff97 	bl	8f00 <targetfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff ff93 	bl	8f00 <targetfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff ff8f 	bl	8f00 <targetfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff ff8b 	bl	8f00 <targetfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff ff87 	bl	8f00 <targetfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff ff83 	bl	8f00 <targetfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 f807 	bl	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f7ff ff7b 	bl	8f00 <targetfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	f7ff bf76 	b\.w	8f00 <targetfn>
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel.s b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel.s
new file mode 100644
index 0000000..2d21bbf
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel.s
@@ -0,0 +1,40 @@
+	.syntax unified
+	.cpu cortex-a8
+	.thumb
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+1:
+        add.w r0, r1, r2
+        bl.w targetfn
+        add.w r0, r1, r2
+        bl.w targetfn
+        add.w r0, r1, r2
+        bl.w targetfn
+        add.w r0, r1, r2
+        bl.w targetfn
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+        .align  3
+        .global _start
+        .thumb
+        .thumb_func
+        .type   _start, %function
+_start:
+	nop
+
+	@ If calling an ARM destination, we *don't* want to create a
+	@ Cortex-A8 stub: the Thumb-to-ARM stub will suffice.
+	bw2
+	bw2
+
+        bx      lr
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl.d b/ld/testsuite/ld-arm/cortex-a8-fix-bl.d
new file mode 100644
index 0000000..50dcd4f
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl.d
@@ -0,0 +1,75 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <_start>:
+    8f00:	bf00      	nop
+    8f02:	eb01 0002 	add\.w	r0, r1, r2
+    8f06:	f7ff fffc 	bl	8f02 <_start\+0x2>
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff fff8 	bl	8f02 <_start\+0x2>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff fff4 	bl	8f02 <_start\+0x2>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff fff0 	bl	8f02 <_start\+0x2>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff fffc 	bl	8f22 <_start\+0x22>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff fff8 	bl	8f22 <_start\+0x22>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff fff4 	bl	8f22 <_start\+0x22>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff fff0 	bl	8f22 <_start\+0x22>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff fffc 	bl	8f42 <_start\+0x42>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff fff8 	bl	8f42 <_start\+0x42>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff fff4 	bl	8f42 <_start\+0x42>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff fff0 	bl	8f42 <_start\+0x42>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff fffc 	bl	8f62 <_start\+0x62>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff fff8 	bl	8f62 <_start\+0x62>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff fff4 	bl	8f62 <_start\+0x62>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff fff0 	bl	8f62 <_start\+0x62>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff fffc 	bl	8f82 <_start\+0x82>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff fff8 	bl	8f82 <_start\+0x82>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff fff4 	bl	8f82 <_start\+0x82>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff fff0 	bl	8f82 <_start\+0x82>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff fffc 	bl	8fa2 <_start\+0xa2>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff fff8 	bl	8fa2 <_start\+0xa2>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff fff4 	bl	8fa2 <_start\+0xa2>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff fff0 	bl	8fa2 <_start\+0xa2>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff fffc 	bl	8fc2 <_start\+0xc2>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff fff8 	bl	8fc2 <_start\+0xc2>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff fff4 	bl	8fc2 <_start\+0xc2>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff fff0 	bl	8fc2 <_start\+0xc2>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff fffc 	bl	8fe2 <_start\+0xe2>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff fff8 	bl	8fe2 <_start\+0xe2>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff fff4 	bl	8fe2 <_start\+0xe2>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 f803 	bl	9008 <_start\+0x108>
+    9002:	4770      	bx	lr
+    9004:	f3af 8000 	nop\.w
+    9008:	f7ff bfeb 	b\.w	8fe2 <_start\+0xe2>
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl.s b/ld/testsuite/ld-arm/cortex-a8-fix-bl.s
new file mode 100644
index 0000000..6e40fb8
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl.s
@@ -0,0 +1,39 @@
+	.syntax unified
+	.cpu cortex-a8
+	.thumb
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+1:
+        add.w r0, r1, r2
+        bl.w 1b
+        add.w r0, r1, r2
+        bl.w 1b
+        add.w r0, r1, r2
+        bl.w 1b
+        add.w r0, r1, r2
+        bl.w 1b
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+        .align  3
+        .global _start
+        .thumb
+        .thumb_func
+        .type   _start, %function
+_start:
+        nop
+
+	@ Trigger Cortex-A8 erratum workaround with bl instructions.
+        bw2
+        bw2
+
+        bx      lr
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-arm.d b/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-arm.d
new file mode 100644
index 0000000..fcb3bab
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-arm.d
@@ -0,0 +1,79 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <targetfn>:
+    8f00:	e12fff1e 	bx	lr
+    8f04:	e320f000 	nop	\{0\}
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff eff8 	blx	8f00 <targetfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff eff4 	blx	8f00 <targetfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff eff0 	blx	8f00 <targetfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff efec 	blx	8f00 <targetfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff efe8 	blx	8f00 <targetfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff efe4 	blx	8f00 <targetfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff efe0 	blx	8f00 <targetfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff efdc 	blx	8f00 <targetfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff efd8 	blx	8f00 <targetfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff efd4 	blx	8f00 <targetfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff efd0 	blx	8f00 <targetfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff efcc 	blx	8f00 <targetfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff efc8 	blx	8f00 <targetfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff efc4 	blx	8f00 <targetfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff efc0 	blx	8f00 <targetfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff efbc 	blx	8f00 <targetfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff efb8 	blx	8f00 <targetfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff efb4 	blx	8f00 <targetfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff efb0 	blx	8f00 <targetfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff efac 	blx	8f00 <targetfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff efa8 	blx	8f00 <targetfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff efa4 	blx	8f00 <targetfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff efa0 	blx	8f00 <targetfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff ef9c 	blx	8f00 <targetfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff ef98 	blx	8f00 <targetfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff ef94 	blx	8f00 <targetfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff ef90 	blx	8f00 <targetfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff ef8c 	blx	8f00 <targetfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff ef88 	blx	8f00 <targetfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff ef84 	blx	8f00 <targetfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 e808 	blx	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f7ff ef7c 	blx	8f00 <targetfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	eaffffba 	b	8f00 <targetfn>
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-thumb.d b/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-thumb.d
new file mode 100644
index 0000000..8cbd3e0
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-thumb.d
@@ -0,0 +1,80 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <targetfn>:
+    8f00:	4770      	bx	lr
+    8f02:	bf00      	nop
+    8f04:	f3af 8000 	nop\.w
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff fff7 	bl	8f00 <targetfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff fff3 	bl	8f00 <targetfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff ffef 	bl	8f00 <targetfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff ffeb 	bl	8f00 <targetfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff ffe7 	bl	8f00 <targetfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff ffe3 	bl	8f00 <targetfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff ffdf 	bl	8f00 <targetfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff ffdb 	bl	8f00 <targetfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff ffd7 	bl	8f00 <targetfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff ffd3 	bl	8f00 <targetfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff ffcf 	bl	8f00 <targetfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff ffcb 	bl	8f00 <targetfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff ffc7 	bl	8f00 <targetfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff ffc3 	bl	8f00 <targetfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff ffbf 	bl	8f00 <targetfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff ffbb 	bl	8f00 <targetfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff ffb7 	bl	8f00 <targetfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff ffb3 	bl	8f00 <targetfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff ffaf 	bl	8f00 <targetfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff ffab 	bl	8f00 <targetfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff ffa7 	bl	8f00 <targetfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff ffa3 	bl	8f00 <targetfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff ff9f 	bl	8f00 <targetfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff ff9b 	bl	8f00 <targetfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff ff97 	bl	8f00 <targetfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff ff93 	bl	8f00 <targetfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff ff8f 	bl	8f00 <targetfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff ff8b 	bl	8f00 <targetfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff ff87 	bl	8f00 <targetfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff ff83 	bl	8f00 <targetfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 f807 	bl	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f7ff ff7b 	bl	8f00 <targetfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	f7ff bf76 	b\.w	8f00 <targetfn>
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel.s b/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel.s
new file mode 100644
index 0000000..efbfb4b
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel.s
@@ -0,0 +1,38 @@
+	.syntax unified
+	.cpu cortex-a8
+	.thumb
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+1:
+        add.w r0, r1, r2
+        blx.w targetfn
+        add.w r0, r1, r2
+        blx.w targetfn
+        add.w r0, r1, r2
+        blx.w targetfn
+        add.w r0, r1, r2
+        blx.w targetfn
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+        .align  3
+        .global _start
+        .thumb
+        .thumb_func
+        .type   _start, %function
+_start:
+	nop
+
+	bw2
+	bw2
+
+        bx      lr
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx.d b/ld/testsuite/ld-arm/cortex-a8-fix-blx.d
new file mode 100644
index 0000000..4805256
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx.d
@@ -0,0 +1,79 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <armfn>:
+    8f00:	e1a02413 	lsl	r2, r3, r4
+    8f04:	e12fff1e 	bx	lr
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff eff8 	blx	8f00 <armfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff eff4 	blx	8f00 <armfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff eff0 	blx	8f00 <armfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff efec 	blx	8f00 <armfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff efe8 	blx	8f00 <armfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff efe4 	blx	8f00 <armfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff efe0 	blx	8f00 <armfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff efdc 	blx	8f00 <armfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff efd8 	blx	8f00 <armfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff efd4 	blx	8f00 <armfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff efd0 	blx	8f00 <armfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff efcc 	blx	8f00 <armfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff efc8 	blx	8f00 <armfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff efc4 	blx	8f00 <armfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff efc0 	blx	8f00 <armfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff efbc 	blx	8f00 <armfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff efb8 	blx	8f00 <armfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff efb4 	blx	8f00 <armfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff efb0 	blx	8f00 <armfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff efac 	blx	8f00 <armfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff efa8 	blx	8f00 <armfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff efa4 	blx	8f00 <armfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff efa0 	blx	8f00 <armfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff ef9c 	blx	8f00 <armfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff ef98 	blx	8f00 <armfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff ef94 	blx	8f00 <armfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff ef90 	blx	8f00 <armfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff ef8c 	blx	8f00 <armfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff ef88 	blx	8f00 <armfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff ef84 	blx	8f00 <armfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 e808 	blx	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f7ff ef7c 	blx	8f00 <armfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	eaffffba 	b	8f00 <armfn>
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx.s b/ld/testsuite/ld-arm/cortex-a8-fix-blx.s
new file mode 100644
index 0000000..5d74024
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx.s
@@ -0,0 +1,44 @@
+	.syntax unified
+	.cpu cortex-a8
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+        add.w r0, r1, r2
+        blx.w armfn
+        add.w r0, r1, r2
+        blx.w armfn
+        add.w r0, r1, r2
+        blx.w armfn
+        add.w r0, r1, r2
+        blx.w armfn
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+	.arm
+        .align  2
+armfn:
+	mov	r2, r3, asl r4
+	bx	lr
+
+        .global _start
+
+	.thumb
+        .thumb_func
+	.align 3
+        .type   _start, %function
+_start:
+        nop
+
+	@ Trigger Cortex-A8 erratum workaround with blx instructions.
+        bw2
+        bw2
+
+        bx      lr
diff --git a/ld/testsuite/ld-arm/cortex-a8-thumb-target.s b/ld/testsuite/ld-arm/cortex-a8-thumb-target.s
new file mode 100644
index 0000000..96c180f
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-thumb-target.s
@@ -0,0 +1,10 @@
+	.syntax unified
+	.cpu cortex-a8
+	.text
+	.thumb
+	.thumb_func
+	.align 3
+	.global targetfn
+	.type targetfn, %function
+targetfn:
+	bx lr