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| author | Alan Modra <amodra@gmail.com> | 2007-11-06 13:49:19 +0000 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2007-11-06 13:49:19 +0000 |
| commit | 102890f04c44b64cf5cef4588267dd9f24086ac7 (patch) | |
| tree | 5c316ac8605bfe000fa18716fe79e98b7a149156 /ld/testsuite | |
| parent | dffc6a6425d286cd29643dcf96b5c2f61e756480 (diff) | |
| download | gdb-102890f04c44b64cf5cef4588267dd9f24086ac7.zip gdb-102890f04c44b64cf5cef4588267dd9f24086ac7.tar.gz gdb-102890f04c44b64cf5cef4588267dd9f24086ac7.tar.bz2 | |
bfd/
* elf64-ppc.c (ppc64_elf_check_relocs): Don't refcount tlsld_got here..
(ppc64_elf_gc_sweep_hook): ..or here..
(ppc64_elf_tls_optimize): ..or here. Make two passes through the
relocs, ensuring that tls_get_addr calls follow gd and ld relocs.
(allocate_dynrelocs): Refcount tlsld_got here.
(ppc64_elf_size_dynamic_sections): Allocate local got and call
allocate_dynrelocs before allocating tlsld_got.
(ppc64_elf_relocate_section): Remove check that a tls_get_addr
call follows gd and ld relocs.
ld/testsuite/
* ld-powerpc/tlsso.d: Update for changed got alloc order.
* ld-powerpc/tlsso.r: Likewise.
Diffstat (limited to 'ld/testsuite')
| -rw-r--r-- | ld/testsuite/ChangeLog | 3 | ||||
| -rw-r--r-- | ld/testsuite/ld-powerpc/tlsso.d | 20 | ||||
| -rw-r--r-- | ld/testsuite/ld-powerpc/tlsso.r | 2 |
3 files changed, 14 insertions, 11 deletions
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index fd417c0..e748cf6 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2007-11-06 Alan Modra <amodra@bigpond.net.au> + * ld-powerpc/tlsso.d: Update for changed got alloc order. + * ld-powerpc/tlsso.r: Likewise. + * ld-powerpc/tlsso32.d: Update for changed got alloc order. 2007-11-05 Alan Modra <amodra@bigpond.net.au> diff --git a/ld/testsuite/ld-powerpc/tlsso.d b/ld/testsuite/ld-powerpc/tlsso.d index 3fa4029..b1149ae 100644 --- a/ld/testsuite/ld-powerpc/tlsso.d +++ b/ld/testsuite/ld-powerpc/tlsso.d @@ -17,40 +17,40 @@ Disassembly of section \.text: .* 4e 80 04 20 bctr .* <_start>: -.* 38 62 80 30 addi r3,r2,-32720 +.* 38 62 80 20 addi r3,r2,-32736 .* 4b ff ff e5 bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) -.* 38 62 80 08 addi r3,r2,-32760 +.* 38 62 80 50 addi r3,r2,-32688 .* 4b ff ff d9 bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) -.* 38 62 80 48 addi r3,r2,-32696 +.* 38 62 80 38 addi r3,r2,-32712 .* 4b ff ff cd bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) -.* 38 62 80 08 addi r3,r2,-32760 +.* 38 62 80 50 addi r3,r2,-32688 .* 4b ff ff c1 bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) .* 39 23 80 40 addi r9,r3,-32704 .* 3d 23 00 00 addis r9,r3,0 .* 81 49 80 48 lwz r10,-32696\(r9\) -.* e9 22 80 40 ld r9,-32704\(r2\) +.* e9 22 80 30 ld r9,-32720\(r2\) .* 7d 49 18 2a ldx r10,r9,r3 -.* e9 22 80 58 ld r9,-32680\(r2\) +.* e9 22 80 48 ld r9,-32696\(r2\) .* 7d 49 6a 2e lhzx r10,r9,r13 .* 89 4d 00 00 lbz r10,0\(r13\) .* 3d 2d 00 00 addis r9,r13,0 .* 99 49 00 00 stb r10,0\(r9\) -.* 38 62 80 18 addi r3,r2,-32744 +.* 38 62 80 08 addi r3,r2,-32760 .* 4b ff ff 8d bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) -.* 38 62 80 08 addi r3,r2,-32760 +.* 38 62 80 50 addi r3,r2,-32688 .* 4b ff ff 81 bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) .* f9 43 80 08 std r10,-32760\(r3\) .* 3d 23 00 00 addis r9,r3,0 .* 91 49 80 10 stw r10,-32752\(r9\) -.* e9 22 80 28 ld r9,-32728\(r2\) +.* e9 22 80 18 ld r9,-32744\(r2\) .* 7d 49 19 2a stdx r10,r9,r3 -.* e9 22 80 58 ld r9,-32680\(r2\) +.* e9 22 80 48 ld r9,-32696\(r2\) .* 7d 49 6b 2e sthx r10,r9,r13 .* e9 4d 00 02 lwa r10,0\(r13\) .* 3d 2d 00 00 addis r9,r13,0 diff --git a/ld/testsuite/ld-powerpc/tlsso.r b/ld/testsuite/ld-powerpc/tlsso.r index 7dcf173..7b2ee14 100644 --- a/ld/testsuite/ld-powerpc/tlsso.r +++ b/ld/testsuite/ld-powerpc/tlsso.r @@ -53,9 +53,9 @@ Relocation section '\.rela\.dyn' at offset .* contains 16 entries: [0-9a-f ]+R_PPC64_TPREL16_HA +0+105f0 \.tdata \+ 30 [0-9a-f ]+R_PPC64_TPREL16_LO +0+105f0 \.tdata \+ 30 [0-9a-f ]+R_PPC64_DTPMOD64 +0+ -[0-9a-f ]+R_PPC64_DTPMOD64 +0+ [0-9a-f ]+R_PPC64_DTPREL64 +0+ [0-9a-f ]+R_PPC64_DTPREL64 +0+18 +[0-9a-f ]+R_PPC64_DTPMOD64 +0+ [0-9a-f ]+R_PPC64_DTPMOD64 +0+ gd \+ 0 [0-9a-f ]+R_PPC64_DTPREL64 +0+ gd \+ 0 [0-9a-f ]+R_PPC64_DTPREL64 +0+50 ld2 \+ 0 |