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| author | Alan Modra <amodra@gmail.com> | 2008-05-07 14:46:44 +0000 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2008-05-07 14:46:44 +0000 |
| commit | 8374f9d4b51c7bb4464875756b1a4b4e9ce742f0 (patch) | |
| tree | 9be50c50e3c11f9a155a9f243921b8d79bf67ae7 /ld/testsuite/ld-spu | |
| parent | 8c0848b5090141528fc24baa8f869252e63b8598 (diff) | |
| download | gdb-8374f9d4b51c7bb4464875756b1a4b4e9ce742f0.zip gdb-8374f9d4b51c7bb4464875756b1a4b4e9ce742f0.tar.gz gdb-8374f9d4b51c7bb4464875756b1a4b4e9ce742f0.tar.bz2 | |
bfd/
* elf32-spu.c (spu_elf_special_sections): Add "._ea".
(spu_elf_relocate_section): Handle relocations against symbols
defined in ._ea specially.
binutils/
* embedspu.sh: Take note of R_SPU_PPU32/64 relocs without a symbol,
and if present, put image in ".data.speelf". Put program handle
in ".data.spehandle".
ld/emulparams/
* elf32_spu.sh (OTHER_SECTIONS): Add "._ea".
* elf32ppc.sh: If building with spu support, put ".data.spehandle"
sections at the start of ".data" and provide a symbol to locate
the directory of embedded spe programs.
ld/testsuite/
* ld-spu/ear.s: Align various sections.
* ld-spu/embed.rd: Update.
Diffstat (limited to 'ld/testsuite/ld-spu')
| -rw-r--r-- | ld/testsuite/ld-spu/ear.s | 3 | ||||
| -rw-r--r-- | ld/testsuite/ld-spu/embed.rd | 24 |
2 files changed, 15 insertions, 12 deletions
diff --git a/ld/testsuite/ld-spu/ear.s b/ld/testsuite/ld-spu/ear.s index ba0be05..724a525 100644 --- a/ld/testsuite/ld-spu/ear.s +++ b/ld/testsuite/ld-spu/ear.s @@ -5,6 +5,7 @@ _start: #test old-style toe _EAR_ syms .section .toe,"a",@nobits + .p2align 4 _EAR_: .space 16 _EAR_bar: @@ -12,6 +13,7 @@ _EAR_bar: #test new-style _EAR_ syms .data + .p2align 4 _EAR_main: .space 16 @@ -21,5 +23,6 @@ _EAR_foo: .space 16 .section .data.blah,"aw",@progbits + .p2align 4 _EAR_blah: .space 16 diff --git a/ld/testsuite/ld-spu/embed.rd b/ld/testsuite/ld-spu/embed.rd index 0ac34da..4fcfe2a 100644 --- a/ld/testsuite/ld-spu/embed.rd +++ b/ld/testsuite/ld-spu/embed.rd @@ -1,16 +1,16 @@ Relocation section '\.rela\.rodata\.speelf' at .* contains 3 entries: - Offset Info Type Sym\. Value Symbol's Name \+ Addend -00000184 00000601 R_PPC_ADDR32 00000000 main \+ 0 -000001a4 00000901 R_PPC_ADDR32 00000000 foo \+ 0 -000001b4 00000701 R_PPC_ADDR32 00000000 blah \+ 0 - -Relocation section '\.rela\.data' at .* contains 2 entries: - Offset Info Type Sym\. Value Symbol's Name \+ Addend -00000004 00000201 R_PPC_ADDR32 00000000 \.rodata\.speelf \+ 0 -00000008 00000401 R_PPC_ADDR32 00000000 \.data\.spetoe \+ 0 + Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend +0+184 .* R_PPC_ADDR32 +0+0 +main \+ 0 +0+1a4 .* R_PPC_ADDR32 +0+0 +foo \+ 0 +0+1b4 .* R_PPC_ADDR32 +0+0 +blah \+ 0 Relocation section '\.rela\.data\.spetoe' at .* contains 2 entries: - Offset Info Type Sym\. Value Symbol's Name \+ Addend -00000004 00000201 R_PPC_ADDR32 00000000 \.rodata\.speelf \+ 0 -00000014 00000a01 R_PPC_ADDR32 00000000 bar \+ 0 + Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend +0+004 .* R_PPC_ADDR32 +0+0 +\.rodata\.speelf \+ 0 +0+014 .* R_PPC_ADDR32 +0+0 +bar \+ 0 + +Relocation section '\.rela\.data\.spehandle' at .* contains 2 entries: + Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend +0+004 .* R_PPC_ADDR32 +0+0 +\.rodata\.speelf \+ 0 +0+008 .* R_PPC_ADDR32 +0+0 +\.data\.spetoe \+ 0 |