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authorAlan Modra <amodra@gmail.com>2003-11-19 03:46:08 +0000
committerAlan Modra <amodra@gmail.com>2003-11-19 03:46:08 +0000
commitaf04c4eaf230f40d0280e4b91ca7c3bbef242ce7 (patch)
tree1b1ab2e2c71640fdb5f6d075854d4bc00e4bee93 /ld/testsuite/ld-powerpc
parent5a46fe39b34aaaab38c776c686549fe7b5beb91f (diff)
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* ld-powerpc/tlsexe32.d: Update for changed symbols from objdump.
* ld-powerpc/tlsso32.d: Likewise.
Diffstat (limited to 'ld/testsuite/ld-powerpc')
-rw-r--r--ld/testsuite/ld-powerpc/tlsexe32.d2
-rw-r--r--ld/testsuite/ld-powerpc/tlsso32.d12
2 files changed, 7 insertions, 7 deletions
diff --git a/ld/testsuite/ld-powerpc/tlsexe32.d b/ld/testsuite/ld-powerpc/tlsexe32.d
index ed4024f..9bd8221 100644
--- a/ld/testsuite/ld-powerpc/tlsexe32.d
+++ b/ld/testsuite/ld-powerpc/tlsexe32.d
@@ -12,7 +12,7 @@ Disassembly of section \.text:
180028c: 80 7f 00 0c lwz r3,12\(r31\)
1800290: 7c 63 12 14 add r3,r3,r2
1800294: 38 7f 00 10 addi r3,r31,16
- 1800298: 48 01 01 85 bl 181041c <__bss_start\+0x48>
+ 1800298: 48 01 01 85 bl 181041c .*
180029c: 3c 62 00 00 addis r3,r2,0
18002a0: 38 63 90 1c addi r3,r3,-28644
18002a4: 3c 62 00 00 addis r3,r2,0
diff --git a/ld/testsuite/ld-powerpc/tlsso32.d b/ld/testsuite/ld-powerpc/tlsso32.d
index d611c26..1e9ba31 100644
--- a/ld/testsuite/ld-powerpc/tlsso32.d
+++ b/ld/testsuite/ld-powerpc/tlsso32.d
@@ -10,13 +10,13 @@ Disassembly of section \.text:
0+538 <_start>:
538: 38 7f 00 1c addi r3,r31,28
- 53c: 48 00 00 01 bl 53c <_start\+0x4>
+ 53c: 48 00 00 01 bl 53c .*
540: 38 7f 00 0c addi r3,r31,12
- 544: 48 00 00 01 bl 544 <_start\+0xc>
+ 544: 48 00 00 01 bl 544 .*
548: 38 7f 00 24 addi r3,r31,36
- 54c: 48 01 01 95 bl 106e0 <__bss_start\+0x48>
+ 54c: 48 01 01 95 bl 106e0 .*
550: 38 7f 00 0c addi r3,r31,12
- 554: 48 01 01 8d bl 106e0 <__bss_start\+0x48>
+ 554: 48 01 01 8d bl 106e0 .*
558: 39 23 80 20 addi r9,r3,-32736
55c: 3d 23 00 00 addis r9,r3,0
560: 81 49 80 24 lwz r10,-32732\(r9\)
@@ -26,9 +26,9 @@ Disassembly of section \.text:
570: 3d 22 00 00 addis r9,r2,0
574: 99 49 00 00 stb r10,0\(r9\)
578: 38 7e 00 14 addi r3,r30,20
- 57c: 48 00 00 01 bl 57c <_start\+0x44>
+ 57c: 48 00 00 01 bl 57c .*
580: 38 7e 00 0c addi r3,r30,12
- 584: 48 00 00 01 bl 584 <_start\+0x4c>
+ 584: 48 00 00 01 bl 584 .*
588: 91 43 80 04 stw r10,-32764\(r3\)
58c: 3d 23 00 00 addis r9,r3,0
590: 91 49 80 08 stw r10,-32760\(r9\)