diff options
| author | Alan Modra <amodra@gmail.com> | 2005-03-16 02:41:28 +0000 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2005-03-16 02:41:28 +0000 |
| commit | cb2d1ef2ae91983d0294ccdf71341f25badd168e (patch) | |
| tree | e67bf565f343f3f3e458ad6e26baa8b0fba4c109 /ld/testsuite/ld-powerpc/tlsexe32.d | |
| parent | 4eb30afc4160a4cb51cf9d7501e96831b956cdc7 (diff) | |
| download | gdb-cb2d1ef2ae91983d0294ccdf71341f25badd168e.zip gdb-cb2d1ef2ae91983d0294ccdf71341f25badd168e.tar.gz gdb-cb2d1ef2ae91983d0294ccdf71341f25badd168e.tar.bz2 | |
bfd/
* elf32-ppc.c (ppc_elf_create_linker_section): Set SEC_LINKER_CREATED
on section. Correct comment, and add FIXME.
(ppc_elf_additional_program_headers): Don't bump header count for
interp. Test SEC_ALLOC, not SEC_LOAD, and don't test size.
(ppc_elf_size_dynamic_sections): Don't strip sdata and sdata2, but
do allocate memory if they need it.
ld/
* emulparams/elf32ppclinux.sh (OTHER_READWRITE_SECTION): Delete.
(OTHER_RELRO_SECTIONS): Set this instead.
ld/testsuite/
* ld-powerpc/tlsexe32.d: Update.
* ld-powerpc/tlsexe32.g: Update.
* ld-powerpc/tlsexe32.r: Update.
* ld-powerpc/tlsexe32.t: Update.
* ld-powerpc/tlsso32.d: Update.
* ld-powerpc/tlsso32.g: Update.
* ld-powerpc/tlsso32.r: Update.
* ld-powerpc/tlsso32.t: Update.
Diffstat (limited to 'ld/testsuite/ld-powerpc/tlsexe32.d')
| -rw-r--r-- | ld/testsuite/ld-powerpc/tlsexe32.d | 66 |
1 files changed, 33 insertions, 33 deletions
diff --git a/ld/testsuite/ld-powerpc/tlsexe32.d b/ld/testsuite/ld-powerpc/tlsexe32.d index b9e8b2e..0df39d5 100644 --- a/ld/testsuite/ld-powerpc/tlsexe32.d +++ b/ld/testsuite/ld-powerpc/tlsexe32.d @@ -8,39 +8,39 @@ Disassembly of section \.text: -01800264 <_start>: - 1800264: 80 7f 00 0c lwz r3,12\(r31\) - 1800268: 7c 63 12 14 add r3,r3,r2 - 180026c: 38 7f 00 10 addi r3,r31,16 - 1800270: 48 01 01 85 bl 18103f4 .* - 1800274: 3c 62 00 00 addis r3,r2,0 - 1800278: 38 63 90 1c addi r3,r3,-28644 - 180027c: 3c 62 00 00 addis r3,r2,0 - 1800280: 38 63 10 00 addi r3,r3,4096 - 1800284: 39 23 80 20 addi r9,r3,-32736 - 1800288: 3d 23 00 00 addis r9,r3,0 - 180028c: 81 49 80 24 lwz r10,-32732\(r9\) - 1800290: 3d 22 00 00 addis r9,r2,0 - 1800294: a1 49 90 2c lhz r10,-28628\(r9\) - 1800298: 89 42 90 30 lbz r10,-28624\(r2\) - 180029c: 3d 22 00 00 addis r9,r2,0 - 18002a0: 99 49 90 34 stb r10,-28620\(r9\) - 18002a4: 3c 62 00 00 addis r3,r2,0 - 18002a8: 38 63 90 00 addi r3,r3,-28672 - 18002ac: 3c 62 00 00 addis r3,r2,0 - 18002b0: 38 63 10 00 addi r3,r3,4096 - 18002b4: 91 43 80 04 stw r10,-32764\(r3\) - 18002b8: 3d 23 00 00 addis r9,r3,0 - 18002bc: 91 49 80 08 stw r10,-32760\(r9\) - 18002c0: 3d 22 00 00 addis r9,r2,0 - 18002c4: b1 49 90 2c sth r10,-28628\(r9\) - 18002c8: a1 42 90 14 lhz r10,-28652\(r2\) - 18002cc: 3d 22 00 00 addis r9,r2,0 - 18002d0: a9 49 90 18 lha r10,-28648\(r9\) +.* <_start>: +.*: 80 7f 00 0c lwz r3,12\(r31\) +.*: 7c 63 12 14 add r3,r3,r2 +.*: 38 7f 00 10 addi r3,r31,16 +.*: 48 01 01 85 bl .*<__tls_get_addr@plt> +.*: 3c 62 00 00 addis r3,r2,0 +.*: 38 63 90 1c addi r3,r3,-28644 +.*: 3c 62 00 00 addis r3,r2,0 +.*: 38 63 10 00 addi r3,r3,4096 +.*: 39 23 80 20 addi r9,r3,-32736 +.*: 3d 23 00 00 addis r9,r3,0 +.*: 81 49 80 24 lwz r10,-32732\(r9\) +.*: 3d 22 00 00 addis r9,r2,0 +.*: a1 49 90 2c lhz r10,-28628\(r9\) +.*: 89 42 90 30 lbz r10,-28624\(r2\) +.*: 3d 22 00 00 addis r9,r2,0 +.*: 99 49 90 34 stb r10,-28620\(r9\) +.*: 3c 62 00 00 addis r3,r2,0 +.*: 38 63 90 00 addi r3,r3,-28672 +.*: 3c 62 00 00 addis r3,r2,0 +.*: 38 63 10 00 addi r3,r3,4096 +.*: 91 43 80 04 stw r10,-32764\(r3\) +.*: 3d 23 00 00 addis r9,r3,0 +.*: 91 49 80 08 stw r10,-32760\(r9\) +.*: 3d 22 00 00 addis r9,r2,0 +.*: b1 49 90 2c sth r10,-28628\(r9\) +.*: a1 42 90 14 lhz r10,-28652\(r2\) +.*: 3d 22 00 00 addis r9,r2,0 +.*: a9 49 90 18 lha r10,-28648\(r9\) Disassembly of section \.got: -01810390 <_GLOBAL_OFFSET_TABLE_-0x4>: - 1810390: 4e 80 00 21 blrl -01810394 <_GLOBAL_OFFSET_TABLE_>: - 1810394: 01 81 02 f0 00 00 00 00 00 00 00 00 00 00 00 00 .* +.* <_GLOBAL_OFFSET_TABLE_-0x4>: +.*: 4e 80 00 21 blrl +.* <_GLOBAL_OFFSET_TABLE_>: +.*: 01 81 02 d0 00 00 00 00 00 00 00 00 00 00 00 00 .* \.\.\. |