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authorRichard Sandiford <rdsandiford@googlemail.com>2007-05-15 12:22:34 +0000
committerRichard Sandiford <rdsandiford@googlemail.com>2007-05-15 12:22:34 +0000
commite68ed250e82e049bff0f537a1a3d3c5afc15854b (patch)
tree3f74159b10c778a5b8f797e7eaf501faba9a881b /ld/testsuite/ld-mips-elf
parentf532a3561cb446a84aa035c217abf841876bb44d (diff)
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ld/testsuite/
* ld-arm/vxworks1.ld: Swap .bss and .data. * ld-arm/vxworks1-lib.rd: Update accordingly. * ld-arm/vxworks1-lib.td: New test. * ld-arm/arm-elf.exp: Run it. * ld-i386/vxworks1.ld: Swap .bss and .data. * ld-i386/vxworks1-lib.rd: Update accordingly. * ld-i386/vxworks1-lib.td: New test. * ld-i386/i386.exp: Run it. * ld-mips-elf/vxworks1.ld: Swap .bss and .data. * ld-mips-elf/vxworks1-lib.rd: Update accordingly. * ld-mips-elf/vxworks1.rd: Likewise. * ld-powerpc/vxworks1.ld: Swap .bss and .data. * ld-powerpc/vxworks1-lib.rd: Update accordingly. * ld-powerpc/vxworks1-lib.td: New test. * ld-powerpc/powerpc.exp: Run it. * ld-sh/vxworks1.ld: Swap .bss and .data. * ld-sh/vxworks1-lib.rd: Update accordingly. * ld-sh/vxworks1-lib.td: New test. * ld-sh/sh-vxworks.exp: Run it. * ld-sparc/vxworks1.ld: Swap .bss and .data. * ld-sparc/vxworks1-lib.rd: Update accordingly. * ld-sparc/vxworks1-lib.td: New test. * ld-sparc/sparc.exp: Run it.
Diffstat (limited to 'ld/testsuite/ld-mips-elf')
-rw-r--r--ld/testsuite/ld-mips-elf/vxworks1-lib.rd10
-rw-r--r--ld/testsuite/ld-mips-elf/vxworks1.ld4
-rw-r--r--ld/testsuite/ld-mips-elf/vxworks1.rd8
3 files changed, 11 insertions, 11 deletions
diff --git a/ld/testsuite/ld-mips-elf/vxworks1-lib.rd b/ld/testsuite/ld-mips-elf/vxworks1-lib.rd
index 225fdea..56bc9a8 100644
--- a/ld/testsuite/ld-mips-elf/vxworks1-lib.rd
+++ b/ld/testsuite/ld-mips-elf/vxworks1-lib.rd
@@ -5,11 +5,11 @@ Relocation section '\.rela\.dyn' at offset .* contains .* entries:
00080c10 .*06 R_MIPS_LO16 00000000 __GOTT_BASE__ \+ 0
00080c14 .*01 R_MIPS_16 00000000 __GOTT_INDEX__ \+ 0
0008141c 00000002 R_MIPS_32 00080c5c
-00081c00 00000002 R_MIPS_32 00080c5c
-00081c04 00000002 R_MIPS_32 00081c00
-00081c08 .*02 R_MIPS_32 00081c08 dglobal \+ 0
-00081c0c .*02 R_MIPS_32 00000000 dexternal \+ 0
-00081424 .*02 R_MIPS_32 00081800 x \+ 0
+00081800 00000002 R_MIPS_32 00080c5c
+00081804 00000002 R_MIPS_32 00081800
+00081808 .*02 R_MIPS_32 00081808 dglobal \+ 0
+0008180c .*02 R_MIPS_32 00000000 dexternal \+ 0
+00081424 .*02 R_MIPS_32 00081c00 x \+ 0
00000000 00000000 R_MIPS_NONE 00000000
#...
Relocation section '\.rela\.plt' at offset .* contains 2 entries:
diff --git a/ld/testsuite/ld-mips-elf/vxworks1.ld b/ld/testsuite/ld-mips-elf/vxworks1.ld
index 74e2c26..8fe3c48 100644
--- a/ld/testsuite/ld-mips-elf/vxworks1.ld
+++ b/ld/testsuite/ld-mips-elf/vxworks1.ld
@@ -23,10 +23,10 @@ SECTIONS
.got : { *(.got.plt) *(.got) }
. = ALIGN (0x400);
- .bss : { *(.bss) *(.dynbss) }
+ .data : { *(.data) }
. = ALIGN (0x400);
- .data : { *(.data) }
+ .bss : { *(.bss) *(.dynbss) }
/DISCARD/ : { *(.reginfo) }
}
diff --git a/ld/testsuite/ld-mips-elf/vxworks1.rd b/ld/testsuite/ld-mips-elf/vxworks1.rd
index f4793a2..f4455f5 100644
--- a/ld/testsuite/ld-mips-elf/vxworks1.rd
+++ b/ld/testsuite/ld-mips-elf/vxworks1.rd
@@ -1,7 +1,7 @@
Relocation section '\.rela\.dyn' at offset .* contains 1 entries:
Offset Info Type Sym.Value Sym. Name \+ Addend
-00081800 .*7e R_MIPS_COPY 00081800 dglobal \+ 0
+00081c00 .*7e R_MIPS_COPY 00081c00 dglobal \+ 0
Relocation section '\.rela\.plt' at offset .* contains 2 entries:
Offset Info Type Sym\.Value Sym\. Name \+ Addend
@@ -16,9 +16,9 @@ Relocation section '\.rela\.text' at offset .* contains 3 entries:
Relocation section '\.rela\.data' at offset .* contains 3 entries:
Offset Info Type Sym.Value Sym. Name \+ Addend
-00081c00 .*02 R_MIPS_32 00081c00 .data \+ 0
-00081c04 .*02 R_MIPS_32 00081800 .bss \+ 0
-00081c08 .*02 R_MIPS_32 00081c04 dexternal \+ 0
+00081800 .*02 R_MIPS_32 00081800 .data \+ 0
+00081804 .*02 R_MIPS_32 00081c00 .bss \+ 0
+00081808 .*02 R_MIPS_32 00081804 dexternal \+ 0
Relocation section '\.rela\.plt\.unloaded' at offset .* contains 8 entries:
Offset Info Type Sym\.Value Sym\. Name \+ Addend