[ bfd/ChangeLog ]

	* elf-bfd.h (local_call_stubs): New member.
	* elfxx-mips.c (FN_STUB_P, CALL_STUB_P, CALL_FP_STUB_P): New macros.
	(mips_elf_calculate_relocation): Handle local mips16 call stubs.
	(mips16_stub_section_p): Rename from mips_elf_stub_section_p, use
	the new stub macros.
	(_bfd_mips_elf_check_relocs): Handle call stubs for code which
	mixes mips16 and mips32 functions. Use mips16_stub_section_p. Mark
	used stubs with SEC_KEEP. Use the new stub macros.

	[ gas/testsuite/ChangeLog ]
	* gas/mips/mips16-intermix.d, gas/mips/mips16-intermix.s: New
	testcase.
	* gas/mips/mips.exp: Run new testcase.

	[ ld/testsuite/ChangeLog ]
	* ld-mips-elf/mips16-intermix-1.s, ld-mips-elf/mips16-intermix-2.s,
	ld-mips-elf/mips16-intermix.d: New testcase.
	* ld-mips-elf/mips-elf.exp (mips16_intermix_test): Run new testcases.

1 files changed, 132 insertions, 0 deletions

diff --git a/ld/testsuite/ld-mips-elf/mips16-intermix.d b/ld/testsuite/ld-mips-elf/mips16-intermix.d
new file mode 100644
index 0000000..5c6ee68
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/mips16-intermix.d
@@ -0,0 +1,132 @@
+
+.*: +file format elf.*mips
+
+SYMBOL TABLE:
+#...
+.* l     F .text	0+[0-9a-f]+ m32_static_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static_l
+.* l     F .text	0+[0-9a-f]+ m32_static1_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_l
+.* l     F .text	0+[0-9a-f]+ m32_static32_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_l
+.* l     F .text	0+[0-9a-f]+ m32_static16_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_l
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_d
+.* l     F .text	0+[0-9a-f]+ m32_static_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static_d
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static_d
+.* l     F .text	0+[0-9a-f]+ m32_static1_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_d
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static1_d
+.* l     F .text	0+[0-9a-f]+ m32_static32_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_d
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static32_d
+.* l     F .text	0+[0-9a-f]+ m32_static16_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_d
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static16_d
+.* l     F .text	0+[0-9a-f]+ m32_static_ld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static_ld
+.* l     F .text	0+[0-9a-f]+ m32_static1_ld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_ld
+.* l     F .text	0+[0-9a-f]+ m32_static32_ld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_ld
+.* l     F .text	0+[0-9a-f]+ m32_static16_ld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_ld
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_dl
+.* l     F .text	0+[0-9a-f]+ m32_static_dl
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static_dl
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static_dl
+.* l     F .text	0+[0-9a-f]+ m32_static1_dl
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_dl
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static1_dl
+.* l     F .text	0+[0-9a-f]+ m32_static32_dl
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_dl
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static32_dl
+.* l     F .text	0+[0-9a-f]+ m32_static16_dl
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_dl
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static16_dl
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_dlld
+.* l     F .text	0+[0-9a-f]+ m32_static_dlld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static_dlld
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static_dlld
+.* l     F .text	0+[0-9a-f]+ m32_static1_dlld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_dlld
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static1_dlld
+.* l     F .text	0+[0-9a-f]+ m32_static32_dlld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_dlld
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static32_dlld
+.* l     F .text	0+[0-9a-f]+ m32_static16_dlld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_dlld
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static16_dlld
+.* l     F .text	0+[0-9a-f]+ m32_static_d_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static_d_l
+.* l     F .text	0+[0-9a-f]+ m32_static1_d_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_d_l
+.* l     F .text	0+[0-9a-f]+ m32_static32_d_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_d_l
+.* l     F .text	0+[0-9a-f]+ m32_static16_d_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_d_l
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_d_d
+.* l     F .text	0+[0-9a-f]+ m32_static_d_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static_d_d
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static_d_d
+.* l     F .text	0+[0-9a-f]+ m32_static1_d_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_d_d
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static1_d_d
+.* l     F .text	0+[0-9a-f]+ m32_static32_d_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_d_d
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static32_d_d
+.* l     F .text	0+[0-9a-f]+ m32_static16_d_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_d_d
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static16_d_d
+#...
+.* l     F .text	0+[0-9a-f]+ __call_stub_m32_static1_d
+.* l     F .text	0+[0-9a-f]+ __call_stub_m16_static1_d
+.* l     F .text	0+[0-9a-f]+ __call_stub_m32_static1_dl
+.* l     F .text	0+[0-9a-f]+ __call_stub_m16_static1_dl
+.* l     F .text	0+[0-9a-f]+ __call_stub_m32_static1_dlld
+.* l     F .text	0+[0-9a-f]+ __call_stub_m16_static1_dlld
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m32_static1_d_l
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m16_static1_d_l
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m32_static1_d_d
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m16_static1_d_d
+.* l     F .text	0+[0-9a-f]+ __call_stub_m32_static16_d
+.* l     F .text	0+[0-9a-f]+ __call_stub_m16_static16_d
+.* l     F .text	0+[0-9a-f]+ __call_stub_m32_static16_dl
+.* l     F .text	0+[0-9a-f]+ __call_stub_m16_static16_dl
+.* l     F .text	0+[0-9a-f]+ __call_stub_m32_static16_dlld
+.* l     F .text	0+[0-9a-f]+ __call_stub_m16_static16_dlld
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m32_static16_d_l
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m16_static16_d_l
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m32_static16_d_d
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m16_static16_d_d
+#...
+.* g     F .text	0+[0-9a-f]+ m32_ld
+#...
+.* g     F .text	0+[0-9a-f]+ m32_d_l
+.* g     F .text	0+[0-9a-f]+ 0xf0 m16_d_d
+.* g     F .text	0+[0-9a-f]+ 0xf0 m16_d
+#...
+.* g     F .text	0+[0-9a-f]+ 0xf0 f16
+#...
+.* g     F .text	0+[0-9a-f]+ m32_d
+#...
+.* g     F .text	0+[0-9a-f]+ 0xf0 m16_dl
+#...
+.* g     F .text	0+[0-9a-f]+ f32
+#...
+.* g     F .text	0+[0-9a-f]+ 0xf0 m16_l
+#...
+.* g     F .text	0+[0-9a-f]+ 0xf0 m16_ld
+#...
+.* g     F .text	0+[0-9a-f]+ 0xf0 m16_dlld
+.* g     F .text	0+[0-9a-f]+ m32_d_d
+#...
+.* g     F .text	0+[0-9a-f]+ m32_dl
+#...
+.* g     F .text	0+[0-9a-f]+ m32_dlld
+#...
+.* g     F .text	0+[0-9a-f]+ 0xf0 m16_d_l
+#...
+.* g     F .text	0+[0-9a-f]+ m32_l
+#pass