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authorMarcus Shawcroft <marcus.shawcroft@arm.com>2014-04-15 17:46:07 +0100
committerMarcus Shawcroft <marcus.shawcroft@arm.com>2014-04-15 17:46:07 +0100
commitfa85fb9a1bf35209a149d07ebefb2a8970e4a27a (patch)
tree4e4455bee3ca3273be5aee30927d9e59ede303ab /ld/testsuite/ld-aarch64
parent35e5d2f0f81d97f9bd41586b1979345072b7989d (diff)
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[AArch64] Fix off by one error in instruction relaxation mask.
The AArch64 TLSDESC to IE relaxation code uses a bit mask intended to ensure that destination register in a relaxed ldr instruction is always X0. The mask has an off by one error resulting in the most significant bit of the destination register being retained in the relaxed instruction. The issue generally appears when the compiler emits TLS accesses code under high register pressure resulting in a broken code sequence.
Diffstat (limited to 'ld/testsuite/ld-aarch64')
-rw-r--r--ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s2
1 files changed, 1 insertions, 1 deletions
diff --git a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s
index c20690c..38b3721 100644
--- a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s
+++ b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s
@@ -4,7 +4,7 @@ var:
.word 2
.text
adrp x0, :tlsdesc:var
- ldr x1, [x0, #:tlsdesc_lo12:var]
+ ldr x17, [x0, #:tlsdesc_lo12:var]
add x0, x0, :tlsdesc_lo12:var
.tlsdesccall var
blr x1