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authorRenlin Li <renlin.li@arm.com>2015-11-03 12:00:10 +0000
committerRenlin Li <renlin.li@arm.com>2015-11-03 12:00:10 +0000
commit1ac688f831d2aaaf7f0cf500056b4aa0ddc4ed4f (patch)
treee32efc64c00913392278032e510082ad3fef8041 /ld/testsuite/ld-aarch64/tls-large-desc-be.d
parentd5f0636bf6fb6b5e54cd405811cfbfcc98fa667b (diff)
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[LD][AARCH64]Add test cases for big-endian.
ld/testsuite 2015-11-03 Renlin Li <renlin.li@arm.com> * ld-aarch64/aarch64-elf.exp: Run newly added test cases. * ld-aarch64/emit-relocs-301.d: Skip aarch64_be. * ld-aarch64/emit-relocs-302.d: Likwise. * ld-aarch64/emit-relocs-310.d: Likwise. * ld-aarch64/emit-relocs-515.d: Likwise. * ld-aarch64/emit-relocs-516.d: Likwise. * ld-aarch64/tls-large-desc.d: Likwise. * ld-aarch64/tls-large-ie.d: Likwise. * ld-aarch64/tls-relax-large-desc-ie.d: Likwise. * ld-aarch64/tls-relax-large-desc-le.d: Likwise. * ld-aarch64/tls-relax-large-gd-ie.d: Likwise. * ld-aarch64/tls-relax-large-gd-le.d: Likwise. * ld-aarch64/emit-relocs-301-be.d: New for aarch64_be. * ld-aarch64/emit-relocs-302-be.d: Likewise. * ld-aarch64/emit-relocs-310-be.d: Likewise. * ld-aarch64/emit-relocs-515-be.d: Likewise. * ld-aarch64/emit-relocs-516-be.d: Likewise. * ld-aarch64/tls-large-desc-be.d: Likewise. * ld-aarch64/tls-large-ie-be.d: Likewise. * ld-aarch64/tls-relax-large-desc-ie-be.d: Likewise. * ld-aarch64/tls-relax-large-desc-le-be.d: Likewise. * ld-aarch64/tls-relax-large-gd-ie-be.d: Likewise. * ld-aarch64/tls-relax-large-gd-le-be.d: Likewise.
Diffstat (limited to 'ld/testsuite/ld-aarch64/tls-large-desc-be.d')
-rw-r--r--ld/testsuite/ld-aarch64/tls-large-desc-be.d39
1 files changed, 39 insertions, 0 deletions
diff --git a/ld/testsuite/ld-aarch64/tls-large-desc-be.d b/ld/testsuite/ld-aarch64/tls-large-desc-be.d
new file mode 100644
index 0000000..2d72da6
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/tls-large-desc-be.d
@@ -0,0 +1,39 @@
+#source: tls-large-desc.s
+#ld: -shared -T relocs.ld -e0
+#notarget: aarch64-*-*
+#objdump: -dr
+#...
+
+Disassembly of section .text:
+
+0000000000010000 \<test\>:
+ +10000: 58000101 ldr x1, 10020 \<test\+0x20\>
+ +10004: 100000e2 adr x2, 10020 \<test\+0x20\>
+ +10008: 8b020032 add x18, x1, x2
+ +1000c: d2a00000 movz x0, #0x0, lsl #16
+ +10010: f2800500 movk x0, #0x28
+ +10014: f8606a41 ldr x1, \[x18,x0\]
+ +10018: 8b000240 add x0, x18, x0
+ +1001c: d63f0020 blr x1
+ +10020: 00000000 .word 0x00000000
+ +10024: 0000ffe0 .word 0x0000ffe0
+
+Disassembly of section .plt:
+
+0000000000010028 <.plt>:
+ +10028: a9bf7bf0 stp x16, x30, \[sp,#-16\]!
+ +1002c: 90000090 adrp x16, 20000 \<_GLOBAL_OFFSET_TABLE_\>
+ +10030: f9401211 ldr x17, \[x16,#32\]
+ +10034: 91008210 add x16, x16, #0x20
+ +10038: d61f0220 br x17
+ +1003c: d503201f nop
+ +10040: d503201f nop
+ +10044: d503201f nop
+ +10048: a9bf0fe2 stp x2, x3, \[sp,#-16\]!
+ +1004c: 90000082 adrp x2, 20000 \<_GLOBAL_OFFSET_TABLE_\>
+ +10050: 90000083 adrp x3, 20000 \<_GLOBAL_OFFSET_TABLE_\>
+ +10054: f9400442 ldr x2, \[x2,#8\]
+ +10058: 91004063 add x3, x3, #0x10
+ +1005c: d61f0040 br x2
+ +10060: d503201f nop
+ +10064: d503201f nop