Add support for OpenRISC 32-bit embedded processor

1 files changed, 37 insertions, 0 deletions

diff --git a/ld/scripttempl/or32.sc b/ld/scripttempl/or32.sc
new file mode 100644
index 0000000..2825b1e
--- /dev/null
+++ b/ld/scripttempl/or32.sc
@@ -0,0 +1,37 @@
+cat <<EOF
+OUTPUT_FORMAT("${OUTPUT_FORMAT}")
+${LIB_SEARCH_DIRS}
+
+SECTIONS
+{
+  .text : {
+    *(.text)
+    ${RELOCATING+ __etext  =  .};
+    ${CONSTRUCTING+ __CTOR_LIST__ = .;}
+    ${CONSTRUCTING+ LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)}
+    ${CONSTRUCTING+ *(.ctors)}
+    ${CONSTRUCTING+ LONG(0)}
+    ${CONSTRUCTING+ __CTOR_END__ = .;}
+    ${CONSTRUCTING+ __DTOR_LIST__ = .;}
+    ${CONSTRUCTING+ LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)}
+    ${CONSTRUCTING+ *(.dtors)}
+    ${CONSTRUCTING+ LONG(0)}
+    ${CONSTRUCTING+ __DTOR_END__ = .;}
+    *(.lit)
+    *(.shdata)
+  }
+  .shbss SIZEOF(.text) + ADDR(.text) :	{
+    *(.shbss)
+  } 
+  .data  : {
+    *(.data)
+    ${RELOCATING+ __edata  =  .};
+  }
+  .bss   SIZEOF(.data) + ADDR(.data) :
+  { 					
+   *(.bss)
+   *(COMMON)
+     ${RELOCATING+ __end = ALIGN(0x8)};
+  }
+}
+EOF