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| author | Sudakshina Das <sudi.das@arm.com> | 2018-11-12 13:26:01 +0000 |
|---|---|---|
| committer | Sudakshina Das <sudi.das@arm.com> | 2018-11-12 13:26:01 +0000 |
| commit | 70f3d23af74dd6a1f90aec8748424cf0b5a953a5 (patch) | |
| tree | 18a41867a7d54c63f487fbb4f1a53e74697852fc /ld/TODO | |
| parent | 503ba600259856b41a88b56922e094ea826df270 (diff) | |
| download | gdb-70f3d23af74dd6a1f90aec8748424cf0b5a953a5.zip gdb-70f3d23af74dd6a1f90aec8748424cf0b5a953a5.tar.gz gdb-70f3d23af74dd6a1f90aec8748424cf0b5a953a5.tar.bz2 | |
[BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds all the system registers that are part of this
extension and are accessible via the MRS/MSR instructions:
- TCO
- TFSRE0_SL1
- TFSR_EL1
- TFSR_EL2
- TFSR_EL3
- TFSR_EL12
- RGSR_EL1
- GCR_EL1
TCO is also accessible with the MSR(immediate) instruction.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
RGSR_EL1 and GCR_EL1.
(aarch64_sys_reg_supported_p): New check for above.
(aarch64_pstatefields): New entry for TCO.
(aarch64_pstatefield_supported_p): New check for above.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test TCO, TFSRE0_SL1,
TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and
GCR_EL1 MSR and MRS.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
Diffstat (limited to 'ld/TODO')
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