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| author | Jim Wilson <jimw@sifive.com> | 2019-08-15 12:01:13 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2019-08-15 12:01:13 -0700 |
| commit | 080a488354d63fec9791a26fadd15e0c5246983d (patch) | |
| tree | 9aa728d8b99659e38b8f1eb05a128c8e60e74cb9 /ld/ChangeLog | |
| parent | db502012fc46b4dd068461aaeafeaa421489c562 (diff) | |
| download | gdb-080a488354d63fec9791a26fadd15e0c5246983d.zip gdb-080a488354d63fec9791a26fadd15e0c5246983d.tar.gz gdb-080a488354d63fec9791a26fadd15e0c5246983d.tar.bz2 | |
RISC-V: Fix lui relaxation issue with code at address 0.
This fixes a problem originally reported at
https://github.com/riscv/riscv-binutils-gdb/issues/173
If you have code linked at address zero, you can have a lui instruction
loading a value 0x800 which gets relaxed to a c.lui which is valid (c.lui 0x1
followed by addi -0x800). Relaxation can reduce the value below 0x800 at which
point the c.lui 0x0 is no longer valid. We can fix this by converting the
c.lui to a c.li which can load 0.
bfd/
* elfnn-riscv.c (perform_relocation) <R_RISCV_RVC_LUI>: If
RISCV_CONST_HIGH_PART (value) is zero, then convert c.lui instruction
to c.li instruction, and use ENCODE_RVC_IMM to set value.
ld/
* testsuite/ld-riscv-elf/c-lui-2.d: New.
* testsuite/ld-riscv-elf/c-lui-2.ld: New.
* testsuite/ld-riscv-elf/c-lui-2.s: New.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run the c-lui-2 test.
Diffstat (limited to 'ld/ChangeLog')
| -rw-r--r-- | ld/ChangeLog | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog index 15ea830..0366b83 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,10 @@ +2019-08-15 Jim Wilson <jimw@sifive.com> + + * testsuite/ld-riscv-elf/c-lui-2.d: New. + * testsuite/ld-riscv-elf/c-lui-2.ld: New. + * testsuite/ld-riscv-elf/c-lui-2.s: New. + * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run the c-lui-2 test. + 2019-08-10 Alan Modra <amodra@gmail.com> * ldlang.h (enum statement_enum): Sort. |