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authorDmitry Selyutin <ghostmansd@gmail.com>2022-07-25 16:10:14 +0300
committerAlan Modra <amodra@gmail.com>2022-08-11 18:38:29 +0930
commit33ae8a3ae31d8ea787d79d2a677d960721ffe682 (patch)
tree6af5ac519b400849a6f7f3e4dc1f2e6df2a8c5dc /include
parentdf4860daad8ffa29e0185e543a0a2aae32f7a925 (diff)
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ppc/svp64: support LibreSOC architecture
This patch adds support for LibreSOC machine and SVP64 extension flag for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit Prefixed instruction format implementing SV. Funded by NLnet through EU Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly submitted via the OpenPOWER Foundation ISA Working Group via the newly-created External RFC Process. For more details, visit https://libre-soc.org.
Diffstat (limited to 'include')
-rw-r--r--include/opcode/ppc.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 7bc6ee2..cf72db6 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -237,6 +237,9 @@ extern const unsigned int spe2_num_opcodes;
/* Opcode is only supported by power10 architecture. */
#define PPC_OPCODE_POWER10 0x400000000000ull
+/* Opcode is only supported by SVP64 extensions (LibreSOC architecture). */
+#define PPC_OPCODE_SVP64 0x800000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)