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| author | Rinat Zelig <rinat@mellanox.com> | 2017-03-27 11:14:30 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2017-03-27 11:14:30 +0100 |
| commit | c0c31e91adc6aabe7c96f02dd51a0f6200a982da (patch) | |
| tree | f8806e3d53e30fbb60346840e7f2970a7fd651e7 /include | |
| parent | cf31b44f3c4d839db0dcce10e0c4cc47d3be4ff1 (diff) | |
| download | gdb-c0c31e91adc6aabe7c96f02dd51a0f6200a982da.zip gdb-c0c31e91adc6aabe7c96f02dd51a0f6200a982da.tar.gz gdb-c0c31e91adc6aabe7c96f02dd51a0f6200a982da.tar.bz2 | |
Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.
opcodes * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
(insert_nps_misc_imm_offset): New function.
(extract_nps_misc imm_offset): New function.
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
gas * testsuite/gas/arc/nps400-12.s: New file.
* testsuite/gas/arc/nps400-12.d: New file.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/arc.h | 14 |
2 files changed, 12 insertions, 6 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 0937552..48f2afc 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2017-03-27 Rinat Zelig <rinat@mellanox.com> + + * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class. + 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h (S390_INSTR_FLAG_VX2): Remove. diff --git a/include/opcode/arc.h b/include/opcode/arc.h index 3914dc0..97db92c 100644 --- a/include/opcode/arc.h +++ b/include/opcode/arc.h @@ -68,6 +68,7 @@ typedef enum LOGICAL, LOOP, MEMORY, + MISC, MOVE, MPY, NET, @@ -77,6 +78,7 @@ typedef enum PUSH, STORE, SUB, + ULTRAIP, XY } insn_class_t; @@ -141,7 +143,7 @@ typedef enum struct arc_opcode { /* The opcode name. */ - const char *name; + const char * name; /* The opcode itself. Those bits which will be filled in with operands are zeroes. */ @@ -371,7 +373,7 @@ extern const unsigned arc_NToperand; struct arc_flag_operand { /* The flag name. */ - const char *name; + const char * name; /* The flag code. */ unsigned code; @@ -453,13 +455,13 @@ struct arc_operand_operation struct arc_pseudo_insn { /* Mnemonic for pseudo/alias insn. */ - const char *mnemonic_p; + const char * mnemonic_p; /* Mnemonic for real instruction. */ - const char *mnemonic_r; + const char * mnemonic_r; /* Flag that will have to be added (if any). */ - const char *flag_r; + const char * flag_r; /* Amount of operands. */ unsigned operand_cnt; @@ -486,7 +488,7 @@ struct arc_aux_reg insn_subclass_t subclass; /* Register name. */ - const char *name; + const char * name; /* Size of the string. */ size_t length; |