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authorJin Ma <jinma@linux.alibaba.com>2023-11-17 14:20:53 +0800
committerChristoph Müllner <christoph.muellner@vrull.eu>2023-12-14 09:54:19 +0100
commit8cb16b68584e14aade8de166c75e1d85e38507bd (patch)
tree05c2821251d0efffa731fa57d99f10d4b6046770 /include
parente20298da05f212c04022c4f1a9991e09e2199c9a (diff)
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RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.
The description of instructions 'th.fmv.hw.x' and 'th.fmv.x.hw' of the XTheadFmv extension in T-Head specific is incorrect, and it also has some impact on the implementation of the binutils, so this patch corrects this. For details see: https://github.com/T-head-Semi/thead-extension-spec/pull/34 gas/ChangeLog: * testsuite/gas/riscv/x-thead-fmv.d: Correct test. * testsuite/gas/riscv/x-thead-fmv.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_FMV_HW_X): Correct coding. (MASK_TH_FMV_HW_X): Likewise. (MATCH_TH_FMV_X_HW): Likewise. (MASK_TH_FMV_X_HW): Likewise. opcodes/ChangeLog: * riscv-opc.c: Correct operands.
Diffstat (limited to 'include')
-rw-r--r--include/opcode/riscv-opc.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9b6dc60..25b7a96 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2515,10 +2515,10 @@
#define MATCH_TH_FSURW 0x5000700b
#define MASK_TH_FSURW 0xf800707f
/* Vendor-specific (T-Head) XTheadFmv instructions. */
-#define MATCH_TH_FMV_HW_X 0x5000100b
-#define MASK_TH_FMV_HW_X 0xfff0707f
-#define MATCH_TH_FMV_X_HW 0x6000100b
-#define MASK_TH_FMV_X_HW 0xfff0707f
+#define MATCH_TH_FMV_X_HW 0xc000100b
+#define MASK_TH_FMV_X_HW 0xfff0707f
+#define MATCH_TH_FMV_HW_X 0xa000100b
+#define MASK_TH_FMV_HW_X 0xfff0707f
/* Vendor-specific (T-Head) XTheadInt instructions. */
#define MATCH_TH_IPOP 0x0050000b
#define MASK_TH_IPOP 0xffffffff