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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-10-28 14:16:39 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-10-28 14:19:42 +0000 |
| commit | dd4a72c859a6896d6df824535590ccbb3631fdd7 (patch) | |
| tree | 7999561fc2abf2203654a950546803413b3930b8 /include | |
| parent | 82503ca7ed8301dc076919d5010bf981e35b1314 (diff) | |
| download | gdb-dd4a72c859a6896d6df824535590ccbb3631fdd7.zip gdb-dd4a72c859a6896d6df824535590ccbb3631fdd7.tar.gz gdb-dd4a72c859a6896d6df824535590ccbb3631fdd7.tar.bz2 | |
aarch64: Add CSR PDEC instruction
This patch adds:
+ New feature +csre to -march command line.
+ New instruction CSR PDEC associated with CSRE feature.
Please note that CSRE system registers were already upstreamed. This patch
should finalize CSRE feature implementation.
CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of
a Call stack record) instruction. Although this instruction has operand
(PDEC) it's instruction's only operand. PDEC forces instruction field Rt
to be set to 0b1111. This results in fixed opcode of the instruction.
gas/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs.
* config/tc-aarch64.c (parse_csr_operand): New operand parser.
(parse_operands): Call to CSR operand parser.
* testsuite/gas/aarch64/csre_csr-invalid.d: New test.
* testsuite/gas/aarch64/csre_csr-invalid.l: New test.
* testsuite/gas/aarch64/csre_csr-invalid.s: New test.
* testsuite/gas/aarch64/csre_csr.d: New test.
* testsuite/gas/aarch64/csre_csr.s: New test.
include/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature.
(enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR.
opcodes/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
* aarch64-tbl.h (CSRE): New CSRE feature handler.
(_CSRE_INSN): New CSRE instruction type.
(struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 6ddcaf9..7d484ad 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -51,6 +51,7 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */ #define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */ #define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */ +#define AARCH64_FEATURE_CSRE (1ULL << 14) /* CSRE feature. */ #define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */ #define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */ #define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */ @@ -432,6 +433,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ + AARCH64_OPND_CSRE_CSR, /* CSRE CSR instruction Rt field. */ }; /* Qualifier constrains an operand. It either specifies a variant of an |