aboutsummaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorMatthew Malcomson <matthew.malcomson@arm.com>2019-05-09 10:29:23 +0100
committerMatthew Malcomson <matthew.malcomson@arm.com>2019-05-09 10:29:23 +0100
commit1be5f94f9c85821287b9ae423f738a8bab499526 (patch)
treea2ff1865a63e3c3082585b950486d9bb05e36b30 /include
parent3c17238bc9fe8a078a6199470291f07bab9c64c8 (diff)
downloadgdb-1be5f94f9c85821287b9ae423f738a8bab499526.zip
gdb-1be5f94f9c85821287b9ae423f738a8bab499526.tar.gz
gdb-1be5f94f9c85821287b9ae423f738a8bab499526.tar.bz2
[binutils][aarch64] New sve_shift_tsz_bhsd iclass.
This new iclass encodes the variant by which is the most significant bit used of bits 23-22:20-19, where those bits are usually part of a given constant operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_shift_tsz_bhsd iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_shift_tsz_bhsd iclass decode.
Diffstat (limited to 'include')
-rw-r--r--include/ChangeLog5
-rw-r--r--include/opcode/aarch64.h1
2 files changed, 6 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog
index 3b389d5..65cdf2b 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,10 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+ * opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd
+ iclass.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
operand.
(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index bd6b845..d1d366b 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -599,6 +599,7 @@ enum aarch64_insn_class
sve_size_sd2,
sve_size_013,
sve_shift_tsz_hsd,
+ sve_shift_tsz_bhsd,
testbranch,
cryptosm3,
cryptosm4,