RISC-V/zfh: Add half-precision floating-point v0.1 instructions.

This patch is porting from the following riscv github,
https://github.com/riscv/riscv-binutils-gdb/commits/rvv-1.0.x-zfh

And here is the draft zfh spec,
https://github.com/riscv/riscv-isa-manual/tree/zfh

bfd/
	* elfxx-riscv.c (riscv_supported_std_z_ext): Added zfh.
	(riscv_implicit_subset): Add implicit f and zicsr for zfh.
gas/
	* config/tc-riscv.c (riscv_extended_subset_supports): Handle
	INSN_CLASS*_ZFH.
	(extended_macro): Handle M_FLH and M_FSH.
	* testsuite/gas/riscv/extended/extended.exp: Updated.
	* testsuite/gas/riscv/extended/fp-zfh-insns.d: New testcase.
	* testsuite/gas/riscv/extended/fp-zfh-insns.s: Likewise.
include/
	* opcode/riscv-opc-extended.h: Added zfh encoding macros
	and DECLARE_INSN.
	* opcode/riscv.h (enum riscv_extended_insn_class): Added INSN_CLASS*_ZFH.
	(enum M_FLH, M_FSH): Added.
opcodes/
	* riscv-opc.c (riscv_draft_opcodes): Added zfh instructions.

2 files changed, 116 insertions, 0 deletions

diff --git a/include/opcode/riscv-opc-extended.h b/include/opcode/riscv-opc-extended.h
index cc7c56c..72fcaf4 100644
--- a/include/opcode/riscv-opc-extended.h
+++ b/include/opcode/riscv-opc-extended.h
@@ -19,6 +19,79 @@
 
 #ifndef RISCV_EXTENDED_ENCODING_H
 #define RISCV_EXTENDED_ENCODING_H
+/* ZFH instruction.  */
+#define MATCH_FLH		0x1007
+#define MASK_FLH		0x707f
+#define MATCH_FSH		0x1027
+#define MASK_FSH		0x707f
+#define MATCH_FADD_H		0x4000053
+#define MASK_FADD_H		0xfe00007f
+#define MATCH_FSUB_H		0xc000053
+#define MASK_FSUB_H		0xfe00007f
+#define MATCH_FMUL_H		0x14000053
+#define MASK_FMUL_H		0xfe00007f
+#define MATCH_FDIV_H		0x1c000053
+#define MASK_FDIV_H		0xfe00007f
+#define MATCH_FSGNJ_H		0x24000053
+#define MASK_FSGNJ_H		0xfe00707f
+#define MATCH_FSGNJN_H		0x24001053
+#define MASK_FSGNJN_H		0xfe00707f
+#define MATCH_FSGNJX_H		0x24002053
+#define MASK_FSGNJX_H		0xfe00707f
+#define MATCH_FMIN_H		0x2c000053
+#define MASK_FMIN_H 		0xfe00707f
+#define MATCH_FMAX_H		0x2c001053
+#define MASK_FMAX_H		0xfe00707f
+#define MATCH_FCVT_S_H		0x40200053
+#define MASK_FCVT_S_H		0xfff0007f
+#define MATCH_FCVT_H_S		0x44000053
+#define MASK_FCVT_H_S		0xfff0007f
+#define MATCH_FCVT_D_H		0x42200053
+#define MASK_FCVT_D_H		0xfff0007f
+#define MATCH_FCVT_H_D		0x44100053
+#define MASK_FCVT_H_D		0xfff0007f
+#define MATCH_FCVT_Q_H		0x46200053
+#define MASK_FCVT_Q_H		0xfff0007f
+#define MATCH_FCVT_H_Q		0x44300053
+#define MASK_FCVT_H_Q		0xfff0007f
+#define MATCH_FSQRT_H		0x5c000053
+#define MASK_FSQRT_H		0xfff0007f
+#define MATCH_FLE_H		0xa4000053
+#define MASK_FLE_H		0xfe00707f
+#define MATCH_FLT_H		0xa4001053
+#define MASK_FLT_H		0xfe00707f
+#define MATCH_FEQ_H		0xa4002053
+#define MASK_FEQ_H		0xfe00707f
+#define MATCH_FCVT_W_H		0xc4000053
+#define MASK_FCVT_W_H		0xfff0007f
+#define MATCH_FCVT_WU_H		0xc4100053
+#define MASK_FCVT_WU_H		0xfff0007f
+#define MATCH_FCVT_L_H		0xc4200053
+#define MASK_FCVT_L_H		0xfff0007f
+#define MATCH_FCVT_LU_H		0xc4300053
+#define MASK_FCVT_LU_H		0xfff0007f
+#define MATCH_FMV_X_H		0xe4000053
+#define MASK_FMV_X_H		0xfff0707f
+#define MATCH_FCLASS_H		0xe4001053
+#define MASK_FCLASS_H		0xfff0707f
+#define MATCH_FCVT_H_W		0xd4000053
+#define MASK_FCVT_H_W		0xfff0007f
+#define MATCH_FCVT_H_WU		0xd4100053
+#define MASK_FCVT_H_WU		0xfff0007f
+#define MATCH_FCVT_H_L		0xd4200053
+#define MASK_FCVT_H_L		0xfff0007f
+#define MATCH_FCVT_H_LU		0xd4300053
+#define MASK_FCVT_H_LU		0xfff0007f
+#define MATCH_FMV_H_X		0xf4000053
+#define MASK_FMV_H_X		0xfff0707f
+#define MATCH_FMADD_H		0x4000043
+#define MASK_FMADD_H		0x600007f
+#define MATCH_FMSUB_H		0x4000047
+#define MASK_FMSUB_H		0x600007f
+#define MATCH_FNMSUB_H		0x400004b
+#define MASK_FNMSUB_H		0x600007f
+#define MATCH_FNMADD_H		0x400004f
+#define MASK_FNMADD_H		0x600007f
 /* RVV instruction.  */
 #define MATCH_VSETVL		0x80007057
 #define MASK_VSETVL		0xfe00707f
@@ -1375,6 +1448,44 @@
 #define MATCH_VFDOTVV		0xe4001057
 #define MASK_VFDOTVV		0xfc00707f
 #endif /* RISCV_EXTENDED_ENCODING_H */
+#ifdef DECLARE_INSN
+DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
+DECLARE_INSN(fsub_h, MATCH_FSUB_D, MASK_FSUB_H)
+DECLARE_INSN(fmul_h, MATCH_FMUL_D, MASK_FMUL_H)
+DECLARE_INSN(fdiv_h, MATCH_FDIV_D, MASK_FDIV_H)
+DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_D, MASK_FSGNJ_H)
+DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_D, MASK_FSGNJN_H)
+DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_D, MASK_FSGNJX_H)
+DECLARE_INSN(fmin_h, MATCH_FMIN_D, MASK_FMIN_H)
+DECLARE_INSN(fmax_h, MATCH_FMAX_D, MASK_FMAX_H)
+DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_D, MASK_FCVT_S_H)
+DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
+DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
+DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
+DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H)
+DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q)
+DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
+DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
+DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
+DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
+DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
+DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
+DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
+DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
+DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
+DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H)
+DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
+DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
+DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
+DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
+DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
+DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
+DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
+DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
+DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
+DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
+DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
+#endif /* DECLARE_INSN */
 #ifdef DECLARE_CSR
 /* Unprivileged extended CSR addresses.  */
 #define CSR_VSTART 0x008
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 5cafcfb..2d9c665 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -501,6 +501,9 @@ enum riscv_extended_insn_class
   INSN_CLASS_V_AND_F,
   INSN_CLASS_V_OR_ZVAMO,
   INSN_CLASS_V_OR_ZVLSSEG,
+  INSN_CLASS_ZFH,
+  INSN_CLASS_D_AND_ZFH,
+  INSN_CLASS_Q_AND_ZFH,
 };
 
 /* This is a list of macro expanded instructions for extended
@@ -509,6 +512,8 @@ enum
 {
   M_VMSGE = M_EXTENDED,
   M_VMSGEU,
+  M_FLH,
+  M_FSH,
 };
 
 /* RVV */