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| author | Nelson Chu <nelson.chu@sifive.com> | 2021-07-22 13:47:07 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-10-28 08:50:29 +0800 |
| commit | 867d7a79f4e5db92f2653530cdde0caa301c7d81 (patch) | |
| tree | 52fde72320c41da441129f1b5e6530608f33213b /include | |
| parent | ffbe01609fbe8adac780396d1c59b70227236918 (diff) | |
| download | gdb-867d7a79f4e5db92f2653530cdde0caa301c7d81.zip gdb-867d7a79f4e5db92f2653530cdde0caa301c7d81.tar.gz gdb-867d7a79f4e5db92f2653530cdde0caa301c7d81.tar.bz2 | |
RISC-V: Support svinval extensions.
https://github.com/riscv/riscv-isa-manual/pull/668/files
There are five new instructions for svinval extension. According to
the above draft spec, two of them (HINVAL.VVMA and HINVAL.GVMA) need
to enable the hypervisor extension. But there is no implementation
of hypervisor extension in mainline, so let's consider the related
issues later.
31..25 24..20 19..15 14..12 11...7 6..2 1..0
sinval.vma 0001011 rs2 rs1 000 00000 11100 11
sfence.w.inval 0001100 00000 00000 000 00000 11100 11
sfence.inval.ir 0001100 00001 00000 000 00000 11100 11
hinval.vvma 0011011 rs2 rs1 000 00000 11100 11
hinval.gvma 0111011 rs2 rs1 000 00000 11100 11
bfd/
* elfxx-riscv.c (riscv_supported_std_s_ext): Added svinval.
gas/
* config/tc-riscv.c (riscv_extended_subset_supports):
Handle INSN_CLASS_SVINVAL.
* testsuite/gas/riscv/extended/extended.exp: Updated.
* testsuite/gas/riscv/extended/svinval.d: Mew testcases.
* testsuite/gas/riscv/extended/svinval.s: Likewise.
include/
* opcode/riscv-opc-extended.h: Added encodings for svinval.
* opcode/riscv.h (riscv_extended_insn_class): Added INSN_CLASS_SVINVAL.
opcodes/
* riscv-opc.c (riscv_draft_opcodes): Added svinval instructions.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc-extended.h | 16 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 |
2 files changed, 17 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc-extended.h b/include/opcode/riscv-opc-extended.h index 72fcaf4..6f664ed 100644 --- a/include/opcode/riscv-opc-extended.h +++ b/include/opcode/riscv-opc-extended.h @@ -1447,6 +1447,17 @@ #define MASK_VDOTUVV 0xfc00707f #define MATCH_VFDOTVV 0xe4001057 #define MASK_VFDOTVV 0xfc00707f +/* Svinval instruction. */ +#define MATCH_SINVAL_VMA 0x16000073 +#define MASK_SINVAL_VMA 0xfe007fff +#define MATCH_SFENCE_W_INVAL 0x18000073 +#define MASK_SFENCE_W_INVAL 0xffffffff +#define MATCH_SFENCE_INVAL_IR 0x18100073 +#define MASK_SFENCE_INVAL_IR 0xffffffff +#define MATCH_HINVAL_VVMA 0x36000073 +#define MASK_HINVAL_VVMA 0xfe007fff +#define MATCH_HINVAL_GVMA 0x76000073 +#define MASK_HINVAL_GVMA 0xfe007fff #endif /* RISCV_EXTENDED_ENCODING_H */ #ifdef DECLARE_INSN DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) @@ -1485,6 +1496,11 @@ DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H) DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H) DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H) DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H) +DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA) +DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL) +DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) +DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA) +DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA) #endif /* DECLARE_INSN */ #ifdef DECLARE_CSR /* Unprivileged extended CSR addresses. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 2d9c665..4c85ac1 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -504,6 +504,7 @@ enum riscv_extended_insn_class INSN_CLASS_ZFH, INSN_CLASS_D_AND_ZFH, INSN_CLASS_Q_AND_ZFH, + INSN_CLASS_SVINVAL, }; /* This is a list of macro expanded instructions for extended |