RISC-V/rvv: Added zve* and zvl* extensions, and clarify the imply rules.

* Recognized zve* and zvl* extensions.
  - zve*: zve64d, zve64f, zve64x, zve32f and zve32x.
  - zvl*: zvl32b, zvl64b, zvl128b, zvl256b, zvl512b, zvl1024b, zvl2048b,
          zvl4096b, zvl8192b, zvl16384b, zvl32768b and zvl65536b.

* Spec said that v requires f and d, zve64d requires d, zve64f and zve32f
  require f.  However, according to the issue 723,
  [https://github.com/riscv/riscv-v-spec/issues/723]

  The general rule is that extension names imply the things they require.
  Therefore, the current imply rules should be as follows,
  - v imply f and d.
  - zve64d imply d.
  - zve64f and zve32f imply f.
  - zvamo imply a.

  Besides, consider the implicit zve and zvl extensions,
  - v imply zve64d and zvl128b.
  - zve64* imply the corresponding zve32*.  For example, zve64f imply zve32f,
    and zve64x imply zve32x.
  - zve*d imply zve*f and zve*x.  For example, zve64d imply zve64f and zve64x.
  - zve*f imply zve*x.  For example, zve64f imply zve64x.
  - zve64* imply zvl64b, and zve32* imply zvl32b.
  - The larger zvl* imply all smaller zvl*.  For example, zvl128b imply zvl64b,
    and zvl32b.

  Therefore, "-march=rv64iv -misa-spec=20191213" will be
  "rv64i2p0_f2p0_d2p0_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0".
  Note: zicsr is the imply extension of f.

* For zve32x, the (segmant) load/store instructions are illegal when EEW is
  64.  Besides, vsew cannot be set to 64 by vsetvli when zve32* is enabled.

* For zvl*b extensions, we also need to enable either v or zve* extensions.
  Otherwise we should issue errors.

bfd/
	* elfxx-riscv.c (riscv_implicit_subsets): Added imply rules for v,
	zve* and zvl*b extensions.
	(riscv_supported_std_z_ext): Added zve* and zvl*b extensions.
	(riscv_parse_check_conflicts): The zvl*b extensions cannot be set
	without v and zve* extensions.
gas/
	* config/tc-riscv.c (riscv_extended_subset_supports): Handle zve*.
	(my_getVsetvliExpression): vsew cannot be set to 64 by vsetvli
	when zve32* is enabled.
	(riscv_ip): The (segmant) loads and stores with EEW 64 cannot be
	used when zve32x is enabled.
	* testsuite/gas/riscv/extended/march-imply-v.d: New testcase.
	* testsuite/gas/riscv/extended/march-imply-zve*.d: Likewise.
	* testsuite/gas/riscv/extended/march-imply-zvl*b.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zve32x.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zve32x.l: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zve32x.s: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zvl.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zvl.l: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Removed
	a-ext from -march since it will be added as implicit ext for zvamo.
	* testsuite/gas/riscv/extended/vector-insns.d: Likewise.
include/
	* opcode/riscv.h: Defined INSN_V_EEW64.
opcodes/
	* riscv-opc.c (riscv_draft_opcodes): Added INSN_V_EEW64 for vector
	loads and stores when the eew encodings are 64.

1 files changed, 2 insertions, 0 deletions

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 6252f69..8cef449 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -446,6 +446,8 @@ extern const struct riscv_opcode riscv_insn_types[];
 
 /* Extended extensions.  */
 
+/* The insn_info fields.  */
+#define INSN_V_EEW64		0x10000000
 /* RVV IMM encodings.  */
 #define EXTRACT_RVV_VI_IMM(x) \
   (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))