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| author | Nelson Chu <nelson.chu@sifive.com> | 2021-06-15 15:05:11 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-10-28 08:50:29 +0800 |
| commit | 626c2b0d3688ffa02d347737f0878dce33245e1c (patch) | |
| tree | 33855fe76a74c9a5a12a2423a0dca0a451204736 /include | |
| parent | 6099b2e4abcb8de39d7d013da0a7f1f2a57f9c80 (diff) | |
| download | gdb-626c2b0d3688ffa02d347737f0878dce33245e1c.zip gdb-626c2b0d3688ffa02d347737f0878dce33245e1c.tar.gz gdb-626c2b0d3688ffa02d347737f0878dce33245e1c.tar.bz2 | |
RISC-V/rvv: Added assembly pseudo and changed assembler mnemonics.
* Added pseudo instruction,
- vfabs.v vd,vs = vfsgnjx.vv vd,vs,vs
* Changed assembler mnemonics, and the older names kept as aliases,
- Changed from vle1.v to vlm.v, and vse1.v to vsm.v.
- Changed from vfredsum and vfwredsum to vfredusum and vfwredusum respectively.
- Changed from vpopc.m to vcpop.m, to be consistent with scalar instruction.
- Changed from vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm.
gas/
* testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l: Updated.
* testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s: Likewise.
* testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d: Likewise.
* testsuite/gas/riscv/extended/vector-insns.d: Likewise.
* testsuite/gas/riscv/extended/vector-insns.s: Likewise.
include/
* opcode/riscv-opc-extended.h: Updated.
opcodes/
* riscv-opc.c: Added pseudo vfabs.v, and changed assembler mnemonics.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc-extended.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/include/opcode/riscv-opc-extended.h b/include/opcode/riscv-opc-extended.h index 3de8809..de9741f 100644 --- a/include/opcode/riscv-opc-extended.h +++ b/include/opcode/riscv-opc-extended.h @@ -99,10 +99,10 @@ #define MASK_VSETIVLI 0xc000707f #define MATCH_VSETVLI 0x00007057 #define MASK_VSETVLI 0x8000707f -#define MATCH_VLE1V 0x02b00007 -#define MASK_VLE1V 0xfff0707f -#define MATCH_VSE1V 0x02b00027 -#define MASK_VSE1V 0xfff0707f +#define MATCH_VLMV 0x02b00007 +#define MASK_VLMV 0xfff0707f +#define MATCH_VSMV 0x02b00027 +#define MASK_VSMV 0xfff0707f #define MATCH_VLE8V 0x00000007 #define MASK_VLE8V 0xfdf0707f #define MATCH_VLE16V 0x00005007 @@ -1359,34 +1359,34 @@ #define MASK_VWREDSUMVS 0xfc00707f #define MATCH_VFREDOSUMVS 0x0c001057 #define MASK_VFREDOSUMVS 0xfc00707f -#define MATCH_VFREDSUMVS 0x04001057 -#define MASK_VFREDSUMVS 0xfc00707f +#define MATCH_VFREDUSUMVS 0x04001057 +#define MASK_VFREDUSUMVS 0xfc00707f #define MATCH_VFREDMAXVS 0x1c001057 #define MASK_VFREDMAXVS 0xfc00707f #define MATCH_VFREDMINVS 0x14001057 #define MASK_VFREDMINVS 0xfc00707f #define MATCH_VFWREDOSUMVS 0xcc001057 #define MASK_VFWREDOSUMVS 0xfc00707f -#define MATCH_VFWREDSUMVS 0xc4001057 -#define MASK_VFWREDSUMVS 0xfc00707f +#define MATCH_VFWREDUSUMVS 0xc4001057 +#define MASK_VFWREDUSUMVS 0xfc00707f #define MATCH_VMANDMM 0x66002057 #define MASK_VMANDMM 0xfe00707f #define MATCH_VMNANDMM 0x76002057 #define MASK_VMNANDMM 0xfe00707f -#define MATCH_VMANDNOTMM 0x62002057 -#define MASK_VMANDNOTMM 0xfe00707f +#define MATCH_VMANDNMM 0x62002057 +#define MASK_VMANDNMM 0xfe00707f #define MATCH_VMXORMM 0x6e002057 #define MASK_VMXORMM 0xfe00707f #define MATCH_VMORMM 0x6a002057 #define MASK_VMORMM 0xfe00707f #define MATCH_VMNORMM 0x7a002057 #define MASK_VMNORMM 0xfe00707f -#define MATCH_VMORNOTMM 0x72002057 -#define MASK_VMORNOTMM 0xfe00707f +#define MATCH_VMORNMM 0x72002057 +#define MASK_VMORNMM 0xfe00707f #define MATCH_VMXNORMM 0x7e002057 #define MASK_VMXNORMM 0xfe00707f -#define MATCH_VPOPCM 0x40082057 -#define MASK_VPOPCM 0xfc0ff07f +#define MATCH_VCPOPM 0x40082057 +#define MASK_VCPOPM 0xfc0ff07f #define MATCH_VFIRSTM 0x4008a057 #define MASK_VFIRSTM 0xfc0ff07f #define MATCH_VMSBFM 0x5000a057 |