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authorNelson Chu <nelson.chu@sifive.com>2021-06-15 17:10:25 +0800
committerNelson Chu <nelson.chu@sifive.com>2021-10-28 08:50:29 +0800
commit3c0675ea93e689148128d28525ab719aeec06f6a (patch)
tree757971a53cb79e13088491605a5cbd76facfccc3 /include
parentd035495d996e8a79a3c29d5e6957ef5310fdc86d (diff)
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RISC-V/rvv: Separate zvamo from v, and removed the zvlsseg extension name.
* Separate zvamo from v extension with v1.0, but keep the implementations. * Removed zvlsseg extension name as the vector segmant loads and stores are required (included) in v extension. * Updated the versions of v and zvamo from draft v0.10 to frozen v1.0. bfd/ * elfxx-riscv.c (riscv_supported_std_z_ext): Removed entry of zvlsseg. gas/ * config/tc-riscv.c (riscv_extended_subset_supports): Changed INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO, and removed INSN_CLASS_V_OR_ZVLSSEG. (riscv_extended_csr_class_check): Updated since the name zvlsseg is removed. * testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Changed -march from rv32iav to rv32ia_zvamo. * testsuite/gas/riscv/extended/vector-insns.d: Changed -march from rv32iafv to rv32iafv_zvamo. include/ * opcode/riscv.h (riscv_extended_insn_class): Changed INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO, and removed INSN_CLASS_V_OR_ZVLSSEG. opcodes/ * riscv-opc.c (riscv_draft_opcodes): Changed INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO since they are separated from v. Also changed INSN_CLASS_V_OR_ZVLSSEG to INSN_CLASS_V as they are included in v.
Diffstat (limited to 'include')
-rw-r--r--include/opcode/riscv.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index bf3fe6a..6252f69 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -515,8 +515,7 @@ enum riscv_extended_insn_class
/* Draft */
INSN_CLASS_V = INSN_CLASS_EXTENDED,
INSN_CLASS_V_AND_F,
- INSN_CLASS_V_OR_ZVAMO,
- INSN_CLASS_V_OR_ZVLSSEG,
+ INSN_CLASS_ZVAMO,
INSN_CLASS_ZFH,
INSN_CLASS_D_AND_ZFH,
INSN_CLASS_Q_AND_ZFH,