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| author | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2016-11-18 10:02:16 +0000 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2016-11-18 10:02:16 +0000 |
| commit | c2c4ff8d52a2cd3263a547b0384692498714aa1b (patch) | |
| tree | 2b85adf0b7eb999a0272cad8dde99c54118c3945 /include | |
| parent | 28617675c264213180a599bb4327bf162029636a (diff) | |
| download | gdb-c2c4ff8d52a2cd3263a547b0384692498714aa1b.zip gdb-c2c4ff8d52a2cd3263a547b0384692498714aa1b.tar.gz gdb-c2c4ff8d52a2cd3263a547b0384692498714aa1b.tar.bz2 | |
[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
Add support for FCMLA and FCADD complex arithmetic SIMD instructions.
FCMLA has an indexed element variant where the index range has to be
treated specially because a complex number takes two elements and the
indexed vector size depends on the other operands.
These complex number SIMD instructions are part of ARMv8.3
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
include/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
(enum aarch64_op): Add OP_FCMLA_ELEM.
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
(aarch64_opcode_table): Add fcmla and fcadd.
(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
* aarch64-asm.c (aarch64_ins_imm_rotate): Define.
* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
* aarch64-dis.c (aarch64_ext_imm_rotate): Define.
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
(operand_general_constraint_met_p): Rotate and index range check.
(aarch64_print_operand): Handle rotate operand.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
* testsuite/gas/aarch64/advsimd-armv8_3.d: New.
* testsuite/gas/aarch64/advsimd-armv8_3.s: New.
* testsuite/gas/aarch64/illegal-fcmla.s: New.
* testsuite/gas/aarch64/illegal-fcmla.l: New.
* testsuite/gas/aarch64/illegal-fcmla.d: New.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 5 |
2 files changed, 11 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 9375bc8..8631956 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,11 @@ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> + * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1, + AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3. + (enum aarch64_op): Add OP_FCMLA_ELEM. + +2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> + * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10. (enum aarch64_insn_class): Add ldst_imm10. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index a35a813..69645d0 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -204,6 +204,9 @@ enum aarch64_opnd AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ + AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */ + AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */ + AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */ AARCH64_OPND_COND, /* Standard condition as the last operand. */ AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ @@ -596,6 +599,8 @@ enum aarch64_op OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z, + OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */ + OP_TOTAL_NUM, /* Pseudo. */ }; |