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| author | Nick Clifton <nickc@redhat.com> | 2016-02-04 09:55:10 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2016-02-04 09:55:10 +0000 |
| commit | c1d9289fef41b82aa22f63f74aa8e730ec898d3c (patch) | |
| tree | e477a2b77b58e8d51a359f02cba511bc00f85873 /include | |
| parent | 1b18aa1e79a0b343087d08075f117e821c33b930 (diff) | |
| download | gdb-c1d9289fef41b82aa22f63f74aa8e730ec898d3c.zip gdb-c1d9289fef41b82aa22f63f74aa8e730ec898d3c.tar.gz gdb-c1d9289fef41b82aa22f63f74aa8e730ec898d3c.tar.bz2 | |
Fix the encoding of the MSP430's RRUX instruction.
PR target/19561
opcdoe * msp430-dis.c (print_insn_msp430): Add a special case for
decoding an RRC instruction with the ZC bit set in the extension
word.
include * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
(RRUX): Synthesise using case 2 rather than 7.
gas * config/tc-msp430.c (msp430_operands): Remove case 7. Use case 2
to handle encoding of RRUX instruction.
* testsuite/gas/msp430/msp430x.s: Add more tests of the extended
shift instructions.
* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/msp430.h | 15 |
2 files changed, 16 insertions, 5 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index cbd40b2..b637fc9 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,9 @@ +2016-02-04 Nick Clifton <nickc@redhat.com> + + PR target/19561 + * opcode/msp430.h (IGNORE_CARRY_BIT): New define. + (RRUX): Synthesise using case 2 rather than 7. + 2016-01-19 John Baldwin <jhb@FreeBSD.org> * elf/common.h (NT_FREEBSD_THRMISC): Define. diff --git a/include/opcode/msp430.h b/include/opcode/msp430.h index 110d7cf..463e5e6 100644 --- a/include/opcode/msp430.h +++ b/include/opcode/msp430.h @@ -35,7 +35,13 @@ struct msp430_operand_s #endif }; -#define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */ +/* Byte operation flag for all instructions. Also used as the + A/L bit in the extension word to indicate a 20-bit operation. */ +#define BYTE_OPERATION (1 << 6) +/* Z/C bit in the extension word. If set the carry bit is ignored + for the duration of the operation, although it may be changed as + a result of the operation. */ +#define IGNORE_CARRY_BIT (1 << 8) struct msp430_opcode_s { @@ -46,7 +52,7 @@ struct msp430_opcode_s int bin_mask; }; -#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask } +#define MSP_INSN(name, fmt, numb, bin, mask) { #name, fmt, numb, bin, mask } static struct msp430_opcode_s msp430_opcodes[] = { @@ -156,7 +162,8 @@ static struct msp430_opcode_s msp430_opcodes[] = MSP_INSN (pushx, -3, 1, 0x1200, 0xff80), MSP_INSN (rrax, -3, 1, 0x1100, 0xff80), - MSP_INSN (rrcx, -3, 1, 0x1000, 0xff80), + MSP_INSN (rrcx, -3, 1, 0x1000, 0xff80), /* Synthesised as RRC but with the Z/C bit clear. */ + MSP_INSN (rrux, -3, 1, 0x1000, 0xff80), /* Synthesised as RRC but with the Z/C bit set. */ MSP_INSN (swpbx, -3, 1, 0x1080, 0xffc0), MSP_INSN (sxtx, -3, 1, 0x1180, 0xffc0), @@ -173,8 +180,6 @@ static struct msp430_opcode_s msp430_opcodes[] = MSP_INSN (rlam, -1, 6, 0x0240, 0xf3e0), MSP_INSN (rrum, -1, 6, 0x0340, 0xf3e0), - MSP_INSN (rrux, -1, 7, 0x0340, 0xffe0), /* Synthesized in terms of RRUM. */ - MSP_INSN (adda, -1, 8, 0x00a0, 0xf0b0), MSP_INSN (cmpa, -1, 8, 0x0090, 0xf0b0), MSP_INSN (suba, -1, 8, 0x00b0, 0xf0b0), |