S12Z: Move opcode header to public include directory.

opcodes/
        * s12z.h: Delete.
	* s12z-dis.c: Adjust path of included file.

include/
        * opcode/s12z.h: New file.

gas/
	* config/tc-s12z.c: Adjust path of included file.

2 files changed, 75 insertions, 0 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index 4b3d549..f663f9b 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2018-07-27  John Darrington <john@darrington.wattle.id.au>
+
+        * opcode/s12z.h: New file.
+
 2018-08-09  Richard Earnshaw  <rearnsha@arm.com>
 
 	* elf/arm.h: Updated comments for e_flags definitions.
diff --git a/include/opcode/s12z.h b/include/opcode/s12z.h
new file mode 100644
index 0000000..7e38ac5
--- /dev/null
+++ b/include/opcode/s12z.h
@@ -0,0 +1,71 @@
+#ifndef S12Z_H
+#define S12Z_H
+
+/* This byte is used to prefix instructions in "page 2" of the opcode
+   space */
+#define PAGE2_PREBYTE (0x1b)
+
+struct reg
+{
+  char      *name;   /* The canonical name of the register */
+  int       bytes;   /* its size, in bytes */
+};
+
+
+/* How many registers do we have.  Actually there are only 13,
+   because CCL and CCH are the low and high bytes of CCW.  But
+   for assemnbly / disassembly purposes they are considered
+   distinct registers. */
+#define S12Z_N_REGISTERS 15
+
+extern const struct reg registers[S12Z_N_REGISTERS];
+
+enum {
+    REG_D2 = 0,
+    REG_D3,
+    REG_D4,
+    REG_D5,
+    REG_D0,
+    REG_D1,
+    REG_D6,
+    REG_D7,
+    REG_X,
+    REG_Y,
+    REG_S,
+    REG_P,
+    REG_CCH,
+    REG_CCL,
+    REG_CCW
+  };
+
+/* Any of the registers d0, d1, ... d7 */
+#define REG_BIT_Dn \
+((0x1U << REG_D2) | \
+ (0x1U << REG_D3) | \
+ (0x1U << REG_D4) | \
+ (0x1U << REG_D5) | \
+ (0x1U << REG_D6) | \
+ (0x1U << REG_D7) | \
+ (0x1U << REG_D0) | \
+ (0x1U << REG_D1))
+
+/* Any of the registers x, y or z */
+#define REG_BIT_XYS \
+((0x1U << REG_X) | \
+ (0x1U << REG_Y) | \
+ (0x1U << REG_S))
+
+/* Any of the registers x, y, z or p */
+#define REG_BIT_XYSP \
+((0x1U << REG_X)  | \
+ (0x1U << REG_Y)  | \
+ (0x1U << REG_S)  | \
+ (0x1U << REG_P))
+
+/* The x register or the y register */
+#define REG_BIT_XY \
+((0x1U << REG_X) | \
+ (0x1U << REG_Y))
+
+
+#endif