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| author | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:52:30 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:52:30 +0100 |
| commit | 0c608d6b62f9164203685ab125b4b3ad113eb26e (patch) | |
| tree | e01cae5bc0e942f357798fcd92160aec3e2521ee /include | |
| parent | 01dbfe4c0e2b832c6b1076e8d373b162e2faa376 (diff) | |
| download | gdb-0c608d6b62f9164203685ab125b4b3ad113eb26e.zip gdb-0c608d6b62f9164203685ab125b4b3ad113eb26e.tar.gz gdb-0c608d6b62f9164203685ab125b4b3ad113eb26e.tar.bz2 | |
[AArch64][SVE 20/32] Add support for tied operands
SVE has some instructions in which the same register appears twice
in the assembly string, once as an input and once as an output.
This patch adds a general mechanism for that.
The patch needs to add new information to the instruction entries.
One option would have been to extend the flags field of the opcode
to 64 bits (since we already rely on 64-bit integers being available
on the host). However, the *_INSN macros mean that it's easy to add
new information as top-level fields without affecting the existing
table entries too much. Going for that option seemed to give slightly
neater code.
include/
* opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
(AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
(_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
(V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
* aarch64-opc.c (aarch64_match_operands_constraint): Check for
tied operands.
gas/
* config/tc-aarch64.c (output_operand_error_record): Handle
AARCH64_OPDE_UNTIED_OPERAND.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 9 |
2 files changed, 14 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 21ddbfd..e6c3dbd 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,10 @@ 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * opcode/aarch64.h (aarch64_opcode): Add a tied_operand field. + (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind. + +2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * opcode/aarch64.h (F_STRICT): New flag. 2016-09-07 Richard Earnshaw <rearnsha@arm.com> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 24a2ddb..d39f10d 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -539,6 +539,10 @@ struct aarch64_opcode /* Flags providing information about this instruction */ uint32_t flags; + /* If nonzero, this operand and operand 0 are both registers and + are required to have the same register number. */ + unsigned char tied_operand; + /* If non-NULL, a function to verify that a given instruction is valid. */ bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn); }; @@ -872,6 +876,10 @@ typedef struct aarch64_inst aarch64_inst; No syntax error, but the operands are not a valid combination, e.g. FMOV D0,S0 + AARCH64_OPDE_UNTIED_OPERAND + The asm failed to use the same register for a destination operand + and a tied source operand. + AARCH64_OPDE_OUT_OF_RANGE Error about some immediate value out of a valid range. @@ -908,6 +916,7 @@ enum aarch64_operand_error_kind AARCH64_OPDE_SYNTAX_ERROR, AARCH64_OPDE_FATAL_SYNTAX_ERROR, AARCH64_OPDE_INVALID_VARIANT, + AARCH64_OPDE_UNTIED_OPERAND, AARCH64_OPDE_OUT_OF_RANGE, AARCH64_OPDE_UNALIGNED, AARCH64_OPDE_REG_LIST, |