aarch64: [SME] Add LD1x, ST1x, LDR and STR instructions

This patch is adding new loads and stores defined by SME instructions.

gas/ChangeLog:

	* config/tc-aarch64.c (parse_sme_address): New parser.
	(parse_sme_za_hv_tiles_operand_with_braces): New parser.
	(parse_sme_za_array): New parser.
	(output_operand_error_record): Print error details if
	present.
	(parse_operands): Support new operands.
	* testsuite/gas/aarch64/sme-5-illegal.d: New test.
	* testsuite/gas/aarch64/sme-5-illegal.l: New test.
	* testsuite/gas/aarch64/sme-5-illegal.s: New test.
	* testsuite/gas/aarch64/sme-5.d: New test.
	* testsuite/gas/aarch64/sme-5.s: New test.
	* testsuite/gas/aarch64/sme-6-illegal.d: New test.
	* testsuite/gas/aarch64/sme-6-illegal.l: New test.
	* testsuite/gas/aarch64/sme-6-illegal.s: New test.
	* testsuite/gas/aarch64/sme-6.d: New test.
	* testsuite/gas/aarch64/sme-6.s: New test.
	* testsuite/gas/aarch64/sme-7-illegal.d: New test.
	* testsuite/gas/aarch64/sme-7-illegal.l: New test.
	* testsuite/gas/aarch64/sme-7-illegal.s: New test.
	* testsuite/gas/aarch64/sme-7.d: New test.
	* testsuite/gas/aarch64/sme-7.s: New test.

include/ChangeLog:

	* opcode/aarch64.h (enum aarch64_opnd): New operands.
	(enum aarch64_insn_class): Added sme_ldr and sme_str.
	(AARCH64_OPDE_UNTIED_IMMS): New operand error kind.

opcodes/ChangeLog:

	* aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter.
	(aarch64_ins_sme_za_list): New inserter.
	(aarch64_ins_sme_za_array): New inserter.
	(aarch64_ins_sme_addr_ri_u4xvl): New inserter.
	* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): Added
	ins_sme_za_list, ins_sme_za_array and ins_sme_addr_ri_u4xvl.
	* aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor.
	(aarch64_ext_sme_za_list): New extractor.
	(aarch64_ext_sme_za_array): New extractor.
	(aarch64_ext_sme_addr_ri_u4xvl): New extractor.
	* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): Added
	ext_sme_za_list, ext_sme_za_array and ext_sme_addr_ri_u4xvl.
	* aarch64-opc.c (operand_general_constraint_met_p):
	(aarch64_match_operands_constraint): Handle sme_ldr, sme_str
	and sme_misc.
	(aarch64_print_operand): New operands supported.
	* aarch64-tbl.h (OP_SVE_QUU): New qualifier.
	(OP_SVE_QZU): New qualifier.
	aarch64-asm-2.c: Regenerate.
	aarch64-dis-2.c: Regenerate.
	aarch64-opc-2.c: Regenerate.

1 files changed, 11 insertions, 1 deletions

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index a224b8a..ea1b495 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -337,7 +337,6 @@ enum aarch64_opnd
   AARCH64_OPND_PRFOP,		/* Prefetch operation.  */
   AARCH64_OPND_BARRIER_PSB,	/* Barrier operand for PSB.  */
   AARCH64_OPND_BTI_TARGET,	/* BTI {<target>}.  */
-
   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
   AARCH64_OPND_SVE_ADDR_RI_S4x32,   /* SVE [<Xn|SP>, #<simm4>*32].  */
   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
@@ -355,6 +354,7 @@ enum aarch64_opnd
   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
+  AARCH64_OPND_SVE_ADDR_RR_LSL4,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4].  */
   AARCH64_OPND_SVE_ADDR_RX,	    /* SVE [<Xn|SP>, <Xm>].  */
   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
@@ -451,6 +451,9 @@ enum aarch64_opnd
   AARCH64_OPND_SME_ZA_HV_idx_dest,	/* SME destination ZA tile vector.  */
   AARCH64_OPND_SME_Pm,		/* SME scalable predicate register, bits [15:13].  */
   AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles.  */
+  AARCH64_OPND_SME_ZA_HV_idx_ldstr,	/* SME destination ZA tile vector.  */
+  AARCH64_OPND_SME_ZA_array,        /* SME ZA[<Wv>{, #<imm>}].  */
+  AARCH64_OPND_SME_ADDR_RI_U4xVL,   /* SME [<Xn|SP>{, #<imm>, MUL VL}].  */
   AARCH64_OPND_TME_UIMM16,	/* TME unsigned 16-bit immediate.  */
   AARCH64_OPND_SM3_IMM2,	/* SM3 encodes lane in bits [13, 14].  */
 };
@@ -616,6 +619,8 @@ enum aarch64_insn_class
   pcreladdr,
   ic_system,
   sme_misc,
+  sme_ldr,
+  sme_str,
   sve_cpy,
   sve_index,
   sve_limm,
@@ -1215,6 +1220,10 @@ struct aarch64_inst
      No syntax error, but the operands are not a valid combination, e.g.
      FMOV D0,S0
 
+   AARCH64_OPDE_UNTIED_IMMS
+     The asm failed to use the same immediate for a destination operand
+     and a tied source operand.
+
    AARCH64_OPDE_UNTIED_OPERAND
      The asm failed to use the same register for a destination operand
      and a tied source operand.
@@ -1255,6 +1264,7 @@ enum aarch64_operand_error_kind
   AARCH64_OPDE_SYNTAX_ERROR,
   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
   AARCH64_OPDE_INVALID_VARIANT,
+  AARCH64_OPDE_UNTIED_IMMS,
   AARCH64_OPDE_UNTIED_OPERAND,
   AARCH64_OPDE_OUT_OF_RANGE,
   AARCH64_OPDE_UNALIGNED,