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| author | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:51:00 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:51:00 +0100 |
| commit | 4989adac848eb8f2fee8b98d9615d2fded22623b (patch) | |
| tree | 037a0e65e4cba64ab1174d6533dbf28187d405fd /include | |
| parent | 73866052f244927457202e4b0d1542bea529878f (diff) | |
| download | gdb-4989adac848eb8f2fee8b98d9615d2fded22623b.zip gdb-4989adac848eb8f2fee8b98d9615d2fded22623b.tar.gz gdb-4989adac848eb8f2fee8b98d9615d2fded22623b.tar.bz2 | |
[AArch64][SVE 13/32] Add an F_STRICT flag
SVE predicate operands can appear in three forms:
1. unsuffixed: "Pn"
2. with a predication type: "Pn/[ZM]"
3. with a size suffix: "Pn.[BHSD]"
No variation is allowed: unsuffixed operands cannot have a (redundant)
suffix, and the suffixes can never be dropped. Unsuffixed Pn are used
in LDR and STR, but they are also used for Pg operands in cases where
the result is scalar and where there is therefore no choice to be made
between "merging" and "zeroing". This means that some Pg operands have
suffixes and others don't.
It would be possible to use context-sensitive parsing to handle
this difference. The tc-aarch64.c code would then raise an error
if the wrong kind of suffix is used for a particular instruction.
However, we get much more user-friendly error messages if we parse
all three forms for all SVE instructions and record the suffix as a
qualifier. The normal qualifier matching code can then report cases
where the wrong kind of suffix is used. This is a slight extension
of existing usage, which really only checks for the wrong choice of
suffix within a particular kind of suffix.
The only catch is a that a "NIL" entry in the qualifier list
specifically means "no suffix should be present" (case 1 above).
NIL isn't a wildcard here. It also means that an instruction that
requires all-NIL qualifiers can fail to match (because a suffix was
supplied when it shouldn't have been); this requires a slight change
to find_best_match.
This patch adds an F_STRICT flag to select this behaviour.
The flag will be set for all SVE instructions. The behaviour
for other instructions doesn't change.
include/
* opcode/aarch64.h (F_STRICT): New flag.
opcodes/
* aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
gas/
* config/tc-aarch64.c (find_best_match): Simplify, allowing an
instruction with all-NIL qualifiers to fail to match.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 4 |
2 files changed, 7 insertions, 1 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 2c922c4..21ddbfd 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + + * opcode/aarch64.h (F_STRICT): New flag. + 2016-09-07 Richard Earnshaw <rearnsha@arm.com> * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 1e38749..24a2ddb 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -598,7 +598,9 @@ extern aarch64_opcode aarch64_opcode_table[]; #define F_OD(X) (((X) & 0x7) << 24) /* Instruction has the field of 'sz'. */ #define F_LSE_SZ (1 << 27) -/* Next bit is 28. */ +/* Require an exact qualifier match, even for NIL qualifiers. */ +#define F_STRICT (1ULL << 28) +/* Next bit is 29. */ static inline bfd_boolean alias_opcode_p (const aarch64_opcode *opcode) |