RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0

SiFive has define as set of flexible instruction for extending vector
coprocessor, it able to encoding opcode like .insn but with predefined
format.

List of instructions:
  sf.vc.x
  sf.vc.i
  sf.vc.vv
  sf.vc.xv
  sf.vc.iv
  sf.vc.fv
  sf.vc.vvv
  sf.vc.xvv
  sf.vc.ivv
  sf.vc.fvv
  sf.vc.vvw
  sf.vc.xvw
  sf.vc.ivw
  sf.vc.fvw
  sf.vc.v.x
  sf.vc.v.i
  sf.vc.v.vv
  sf.vc.v.xv
  sf.vc.v.iv
  sf.vc.v.fv
  sf.vc.v.vvv
  sf.vc.v.xvv
  sf.vc.v.ivv
  sf.vc.v.fvv
  sf.vc.v.vvw
  sf.vc.v.xvw
  sf.vc.v.ivw
  sf.vc.v.fvw

Spec of Xsfvcp
https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software

Co-authored-by: Hau Hsu <hau.hsu@sifive.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>

2 files changed, 64 insertions, 0 deletions

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 1af8475..9b6dc60 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2974,6 +2974,63 @@
 #define MASK_VT_MASKC 0xfe00707f
 #define MATCH_VT_MASKCN 0x707b
 #define MASK_VT_MASKCN 0xfe00707f
+/* Vendor-specific (SiFive) vector coprocessor interface instructions.  */
+#define MATCH_SF_VC_X 0x0200405b
+#define MASK_SF_VC_X 0xf200707f
+#define MATCH_SF_VC_V_X 0x0000405b
+#define MASK_SF_VC_V_X 0xf200707f
+#define MATCH_SF_VC_I 0x0200305b
+#define MASK_SF_VC_I 0xf200707f
+#define MATCH_SF_VC_V_I 0x0000305b
+#define MASK_SF_VC_V_I 0xf200707f
+#define MATCH_SF_VC_VV 0x2200005b
+#define MASK_SF_VC_VV 0xf200707f
+#define MATCH_SF_VC_V_VV 0x2000005b
+#define MASK_SF_VC_V_VV 0xf200707f
+#define MATCH_SF_VC_XV 0x2200405b
+#define MASK_SF_VC_XV 0xf200707f
+#define MATCH_SF_VC_V_XV 0x2000405b
+#define MASK_SF_VC_V_XV 0xf200707f
+#define MATCH_SF_VC_IV 0x2200305b
+#define MASK_SF_VC_IV 0xf200707f
+#define MATCH_SF_VC_V_IV 0x2000305b
+#define MASK_SF_VC_V_IV 0xf200707f
+#define MATCH_SF_VC_FV 0x2a00505b
+#define MASK_SF_VC_FV 0xfa00707f
+#define MATCH_SF_VC_V_FV 0x2800505b
+#define MASK_SF_VC_V_FV 0xfa00707f
+#define MATCH_SF_VC_VVV 0xa200005b
+#define MASK_SF_VC_VVV 0xf200707f
+#define MATCH_SF_VC_V_VVV 0xa000005b
+#define MASK_SF_VC_V_VVV 0xf200707f
+#define MATCH_SF_VC_XVV 0xa200405b
+#define MASK_SF_VC_XVV 0xf200707f
+#define MATCH_SF_VC_V_XVV 0xa000405b
+#define MASK_SF_VC_V_XVV 0xf200707f
+#define MATCH_SF_VC_IVV 0xa200305b
+#define MASK_SF_VC_IVV 0xf200707f
+#define MATCH_SF_VC_V_IVV 0xa000305b
+#define MASK_SF_VC_V_IVV 0xf200707f
+#define MATCH_SF_VC_FVV 0xaa00505b
+#define MASK_SF_VC_FVV 0xfa00707f
+#define MATCH_SF_VC_V_FVV 0xa800505b
+#define MASK_SF_VC_V_FVV 0xfa00707f
+#define MATCH_SF_VC_VVW 0xf200005b
+#define MASK_SF_VC_VVW 0xf200707f
+#define MATCH_SF_VC_V_VVW 0xf000005b
+#define MASK_SF_VC_V_VVW 0xf200707f
+#define MATCH_SF_VC_XVW 0xf200405b
+#define MASK_SF_VC_XVW 0xf200707f
+#define MATCH_SF_VC_V_XVW 0xf000405b
+#define MASK_SF_VC_V_XVW 0xf200707f
+#define MATCH_SF_VC_IVW 0xf200305b
+#define MASK_SF_VC_IVW 0xf200707f
+#define MATCH_SF_VC_V_IVW 0xf000305b
+#define MASK_SF_VC_V_IVW 0xf200707f
+#define MATCH_SF_VC_FVW 0xfa00505b
+#define MASK_SF_VC_FVW 0xfa00707f
+#define MATCH_SF_VC_V_FVW 0xf800505b
+#define MASK_SF_VC_V_FVW 0xfa00707f
 /* Unprivileged Counter/Timers CSR addresses.  */
 #define CSR_CYCLE 0xc00
 #define CSR_TIME 0xc01
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 132d686..6687b43 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -331,6 +331,12 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define NVECR 32
 #define NVECM 1
 
+/* SiFive fields.  */
+#define OP_MASK_XSO2            0x3
+#define OP_SH_XSO2              26
+#define OP_MASK_XSO1            0x1
+#define OP_SH_XSO1              26
+
 /* ABI names for selected x-registers.  */
 
 #define X_RA 1
@@ -471,6 +477,7 @@ enum riscv_insn_class
   INSN_CLASS_XTHEADVECTOR,
   INSN_CLASS_XTHEADZVAMO,
   INSN_CLASS_XVENTANACONDOPS,
+  INSN_CLASS_XSFVCP,
 };
 
 /* This structure holds information for a particular instruction.  */