This is a series of patches that add support for the SPARC M7 cpu to

binutils.  They were discussed and approved here:

  https://sourceware.org/ml/binutils/2014-10/msg00038.html

4 files changed, 78 insertions, 2 deletions

diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 7e92493..17978ba 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,18 @@
+2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+	* sparc.h (Tag_GNU_Sparc_HWCAPS2): New object attribute.
+	(ELF_SPARC_HWCAP2_FJATHPLUS): New HWCAP2 bitmask value.
+	(ELF_SPARC_HWCAP2_VIS3B): Likewise.
+	(ELF_SPARC_HWCAP2_ADP): Likewise.
+	(ELF_SPARC_HWCAP2_SPARC5): Likewise.
+	(ELF_SPARC_HWCAP2_MWAIT): Likewise.
+	(ELF_SPARC_HWCAP2_XMPMUL): Likewise.
+	(ELF_SPARC_HWCAP2_XMONT): Likewise.
+	(ELF_SPARC_HWCAP2_NSEC): Likewise.
+	(ELF_SPARC_HWCAP2_FJATHHPC): Likewise.
+	(ELF_SPARC_HWCAP2_FJDES): Likewise.
+	(ELF_SPARC_HWCAP2_FJAES): Likewise.
+
 2014-10-08  Will Newton  <will.newton@linaro.org>
 
 	* aarch64.h: Sync up relocations with ABI release 1.0.
diff --git a/include/elf/sparc.h b/include/elf/sparc.h
index 9bfc27f..d41ba35 100644
--- a/include/elf/sparc.h
+++ b/include/elf/sparc.h
@@ -190,9 +190,19 @@ enum
 {
   /* 0-3 are generic.  */
   Tag_GNU_Sparc_HWCAPS = 4,
+  Tag_GNU_Sparc_HWCAPS2 = 8
 };
 
-/* These values match the AV_SPARC_* hwcap bits defined under Solaris.  */
+/* Generally speaking the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_*
+   values match the AV_SPARC_* and AV2_SPARC_* bits respectively.
+
+   However Solaris 11 introduced a backwards-incompatible change
+   deprecating the RANDOM, TRANS and ASI_CACHE_SPARING bits in the
+   AT_SUNW_CAP_HW1 flags, reusing the bits for the unrelated hwcaps
+   FJATHHPC, FJDES and FJAES respectively.  In GNU/Linux we opted to
+   keep the old hwcaps in Tag_GNU_Sparc_HWCAPS and allocate bits for
+   FJATHHPC, FJDES and JFAES in Tag_GNU_Sparc_HWCAPS2.  */
+
 #define ELF_SPARC_HWCAP_MUL32	0x00000001 /* umul/umulcc/smul/smulcc insns */
 #define ELF_SPARC_HWCAP_DIV32	0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
 #define ELF_SPARC_HWCAP_FSMULD	0x00000004 /* 'fsmuld' insn */
@@ -226,4 +236,17 @@ enum
 #define ELF_SPARC_HWCAP_CBCOND	0x10000000 /* Compare and Branch insns */
 #define ELF_SPARC_HWCAP_CRC32C	0x20000000 /* CRC32C insn */
 
+#define ELF_SPARC_HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */
+#define ELF_SPARC_HWCAP2_VIS3B     0x00000002 /* VIS3 present on multiple chips */
+#define ELF_SPARC_HWCAP2_ADP       0x00000004 /* Application Data Protection */
+#define ELF_SPARC_HWCAP2_SPARC5    0x00000008 /* The 29 new fp and sub instructions */
+#define ELF_SPARC_HWCAP2_MWAIT     0x00000010 /* mwait instruction and load/monitor ASIs */
+#define ELF_SPARC_HWCAP2_XMPMUL    0x00000020 /* XOR multiple precision multiply */
+#define ELF_SPARC_HWCAP2_XMONT     0x00000040 /* XOR Montgomery mult/sqr instructions */
+#define ELF_SPARC_HWCAP2_NSEC      \
+                                   0x00000080 /* pause insn with support for nsec timings */
+#define ELF_SPARC_HWCAP2_FJATHHPC  0x00001000 /* Fujitsu HPC instrs */
+#define ELF_SPARC_HWCAP2_FJDES     0x00002000 /* Fujitsu DES instrs */
+#define ELF_SPARC_HWCAP2_FJAES     0x00010000 /* Fujitsu AES instrs */
+
 #endif /* _ELF_SPARC_H */
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index e16393f..d378910 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,23 @@
+2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+	* sparc.h (sparc_opcode): new field `hwcaps2'.
+	(HWCAP2_FJATHPLUS): New define.
+	(HWCAP2_VIS3B): Likewise.
+	(HWCAP2_ADP): Likewise.
+	(HWCAP2_SPARC5): Likewise.
+	(HWCAP2_MWAIT): Likewise.
+	(HWCAP2_XMPMUL): Likewise.
+	(HWCAP2_XMONT): Likewise.
+	(HWCAP2_NSEC): Likewise.
+	(HWCAP2_FJATHHPC): Likewise.
+	(HWCAP2_FJDES): Likewise.
+	(HWCAP2_FJAES): Likewise.
+	Document the new operand kind `{', corresponding to the mcdper
+	ancillary state register.
+	Document the new operand kind }, which represents frsd floating
+	point registers (double precision) which must be the same than
+	frs1 in its containing instruction.
+
 2014-09-16  Kuan-Lin Chen <kuanlinchentw@gmail.com>
 
         * nds32.h: Add new opcode declaration.
diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index b80876a..cf4ff1c 100644
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -100,6 +100,7 @@ typedef struct sparc_opcode
   /* This was called "delayed" in versions before the flags.  */
   unsigned int flags;
   unsigned int hwcaps;
+  unsigned int hwcaps2;
   short architecture;	/* Bitmask of sparc_opcode_arch_val's.  */
 } sparc_opcode;
 
@@ -115,7 +116,8 @@ typedef struct sparc_opcode
 
 #define F_PREF_ALIAS	(F_ALIAS|F_PREFERRED)
 
-/* These must match the HWCAP_* values precisely.  */
+/* These must match the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_*
+   values precisely.  See include/elf/sparc.h.  */
 #define HWCAP_MUL32	0x00000001 /* umul/umulcc/smul/smulcc insns */
 #define HWCAP_DIV32	0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
 #define HWCAP_FSMULD	0x00000004 /* 'fsmuld' insn */
@@ -148,6 +150,20 @@ typedef struct sparc_opcode
 #define HWCAP_CBCOND	0x10000000 /* Compare and Branch insns */
 #define HWCAP_CRC32C	0x20000000 /* CRC32C insn */
 
+#define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */
+#define HWCAP2_VIS3B     0x00000002 /* VIS3 present on multiple chips */
+#define HWCAP2_ADP       0x00000004 /* Application Data Protection */
+#define HWCAP2_SPARC5    0x00000008 /* The 29 new fp and sub instructions */
+#define HWCAP2_MWAIT     0x00000010 /* mwait instruction and load/monitor ASIs */
+#define HWCAP2_XMPMUL    0x00000020 /* XOR multiple precision multiply */
+#define HWCAP2_XMONT     0x00000040 /* XOR Montgomery mult/sqr instructions */
+#define HWCAP2_NSEC      \
+                         0x00000080 /* pause insn with support for nsec timings */
+#define HWCAP2_FJATHHPC  0x00001000 /* Fujitsu HPC instrs */
+#define HWCAP2_FJDES     0x00002000 /* Fujitsu DES instrs */
+#define HWCAP2_FJAES     0x00010000 /* Fujitsu AES instrs */
+
+
 /* All sparc opcodes are 32 bits, except for the `set' instruction (really a
    macro), which is 64 bits. It is handled as a special case.
 
@@ -173,6 +189,7 @@ typedef struct sparc_opcode
 	g	frsd floating point register.
 	H	frsd floating point register (double/even).
 	J	frsd floating point register (quad/multiple of 4).
+	}       frsd floating point register (double/even) that is == frs2
 	b	crs1 coprocessor register
 	c	crs2 coprocessor register
 	D	crsd coprocessor register
@@ -214,6 +231,7 @@ typedef struct sparc_opcode
 	s	%fprs. (v9)
 	P	%pc.  (v9)
 	W	%tick.	(v9)
+	{	%mcdper. (v9b)
 	o	%asi. (v9)
 	6	%fcc0. (v9)
 	7	%fcc1. (v9)