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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-15 17:21:39 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-09 10:16:40 +0000 |
| commit | a9e2cefdf00202e0ba59825bd66a01ec41ac3ed0 (patch) | |
| tree | b62a75e4faa6bd99b6af833302c239d1457d2e74 /include | |
| parent | 92d8946670571118cccdbcd36d35300af33da4af (diff) | |
| download | gdb-a9e2cefdf00202e0ba59825bd66a01ec41ac3ed0.zip gdb-a9e2cefdf00202e0ba59825bd66a01ec41ac3ed0.tar.gz gdb-a9e2cefdf00202e0ba59825bd66a01ec41ac3ed0.tar.bz2 | |
aarch64: Implement TLBIP 128-bit instruction
The addition of 128-bit page table descriptors and, with it, the
addition of 128-bit system registers for these means that special
"invalidate translation table entry" instructions are needed to cope
with the new 128-bit model. This is introduced with the `tlbpi'
instruction, implemented here.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index b81475f..768caec 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -566,6 +566,7 @@ enum aarch64_opnd AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ + AARCH64_OPND_SYSREG_TLBIP, /* System register <tlbip_op> operand. */ AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */ AARCH64_OPND_BARRIER, /* Barrier operand. */ AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */ |