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| author | Jan Beulich <jbeulich@suse.com> | 2022-10-04 09:46:11 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2022-10-04 09:46:11 +0200 |
| commit | bb996692bd9654d6f2345ab65742796d5fde6829 (patch) | |
| tree | ed55ad57f923ce14e22d3250d24971c80c453cd6 /include | |
| parent | 8c07e983a28cc05edb87882a33c072c0cdfdedc3 (diff) | |
| download | gdb-bb996692bd9654d6f2345ab65742796d5fde6829.zip gdb-bb996692bd9654d6f2345ab65742796d5fde6829.tar.gz gdb-bb996692bd9654d6f2345ab65742796d5fde6829.tar.bz2 | |
RISC-V/gas: allow generating up to 176-bit instructions with .insn
For the time being simply utilize O_big to avoid widening other fields,
bypassing append_insn() etc.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index dd2569f..9417dcf 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -37,6 +37,9 @@ static inline unsigned int riscv_insn_length (insn_t insn) return 6; if ((insn & 0x7f) == 0x3f) /* 64-bit instructions. */ return 8; + /* 80- ... 176-bit instructions. */ + if ((insn & 0x7f) == 0x7f && (insn & 0x7000) != 0x7000) + return 10 + ((insn >> 11) & 0xe); /* Longer instructions not supported at the moment. */ return 2; } |