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author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-10-08 13:58:11 +0000 |
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committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-10-14 05:21:38 +0000 |
commit | 3d9d92c22f6dd2a44f7d4e0d11c0671903e2387f (patch) | |
tree | 5345f72173ed84d3670fb04f7e5fc535eb6d9a0a /include | |
parent | 27fb6a1a7fcd047e7d01bef8e3c12ed67bc7aed0 (diff) | |
download | gdb-3d9d92c22f6dd2a44f7d4e0d11c0671903e2387f.zip gdb-3d9d92c22f6dd2a44f7d4e0d11c0671903e2387f.tar.gz gdb-3d9d92c22f6dd2a44f7d4e0d11c0671903e2387f.tar.bz2 |
RISC-V: Move certain arrays to riscv-opc.c
This is a part of small tidying (declare tables in riscv-opc.c).
include/ChangeLog:
* opcode/riscv.h (riscv_rm, riscv_pred_succ): Move declarations to
opcodes/riscv-opc.c. New non-static definitions.
opcodes/ChangeLog:
* riscv-opc.c (riscv_rm, riscv_pred_succ): Move from
include/opcode/riscv.h. Add description.
Diffstat (limited to 'include')
-rw-r--r-- | include/opcode/riscv.h | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f173a2e..dddabfd 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -46,17 +46,6 @@ static inline unsigned int riscv_insn_length (insn_t insn) return 2; } -static const char * const riscv_rm[8] = -{ - "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" -}; - -static const char * const riscv_pred_succ[16] = -{ - 0, "w", "r", "rw", "o", "ow", "or", "orw", - "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw" -}; - #define RVC_JUMP_BITS 11 #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN) @@ -555,6 +544,8 @@ extern const char * const riscv_gpr_names_numeric[NGPR]; extern const char * const riscv_gpr_names_abi[NGPR]; extern const char * const riscv_fpr_names_numeric[NFPR]; extern const char * const riscv_fpr_names_abi[NFPR]; +extern const char * const riscv_rm[8]; +extern const char * const riscv_pred_succ[16]; extern const char * const riscv_vecr_names_numeric[NVECR]; extern const char * const riscv_vecm_names_numeric[NVECM]; extern const char * const riscv_vsew[8]; |